forked from Minki/linux
53b74ed2d0
This reverts commit5ddc7bd43c("mtd: atmel_nand: Support variable RB_EDGE interrupts") Because for current SoCs, the RB_EDGE3(i.e. bit 27) of HSMC_SR register does not exist, the RB_EDGE0 (i.e. bit 24) is the ready/busy line edge status bit. It is a datasheet bug. Cc: <stable@vger.kernel.org> Fixes: commit5ddc7bd43c("mtd: atmel_nand: Support variable RB_EDGE interrupts") Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
117 lines
3.8 KiB
Plaintext
117 lines
3.8 KiB
Plaintext
Atmel NAND flash
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Required properties:
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- compatible: The possible values are:
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"atmel,at91rm9200-nand"
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"atmel,sama5d2-nand"
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"atmel,sama5d4-nand"
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- reg : should specify localbus address and size used for the chip,
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and hardware ECC controller if available.
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If the hardware ECC is PMECC, it should contain address and size for
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PMECC and PMECC Error Location controller.
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The PMECC lookup table address and size in ROM is optional. If not
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specified, driver will build it in runtime.
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- atmel,nand-addr-offset : offset for the address latch.
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- atmel,nand-cmd-offset : offset for the command latch.
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- #address-cells, #size-cells : Must be present if the device has sub-nodes
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representing partitions.
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- gpios : specifies the gpio pins to control the NAND device. detect is an
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optional gpio and may be set to 0 if not present.
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Optional properties:
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- atmel,nand-has-dma : boolean to support dma transfer for nand read/write.
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- nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
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Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
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"soft_bch".
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- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
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capable of BCH encoding and decoding, on devices where it is present.
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- atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
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Controller. Supported values are: 2, 4, 8, 12, 24. If the compatible string
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is "atmel,sama5d2-nand", 32 is also valid.
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- atmel,pmecc-sector-size : sector size for ECC computation. Supported values
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are: 512, 1024.
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- atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
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for different sector size. First one is for sector size 512, the next is for
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sector size 1024. If not specified, driver will build the table in runtime.
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- nand-bus-width : 8 or 16 bus width if not present 8
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- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
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Nand Flash Controller(NFC) is an optional sub-node
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Required properties:
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- compatible : "atmel,sama5d3-nfc".
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- reg : should specify the address and size used for NFC command registers,
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NFC registers and NFC SRAM. NFC SRAM address and size can be absent
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if don't want to use it.
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- clocks: phandle to the peripheral clock
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Optional properties:
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- atmel,write-by-sram: boolean to enable NFC write by SRAM.
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Examples:
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nand0: nand@40000000,0 {
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compatible = "atmel,at91rm9200-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x40000000 0x10000000
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0xffffe800 0x200
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>;
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atmel,nand-addr-offset = <21>; /* ale */
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atmel,nand-cmd-offset = <22>; /* cle */
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nand-on-flash-bbt;
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nand-ecc-mode = "soft";
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gpios = <&pioC 13 0 /* rdy */
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&pioC 14 0 /* nce */
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0 /* cd */
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>;
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partition@0 {
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...
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};
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};
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/* for PMECC supported chips */
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nand0: nand@40000000 {
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compatible = "atmel,at91rm9200-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = < 0x40000000 0x10000000 /* bus addr & size */
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0xffffe000 0x00000600 /* PMECC addr & size */
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0xffffe600 0x00000200 /* PMECC ERRLOC addr & size */
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0x00100000 0x00100000 /* ROM addr & size */
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>;
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atmel,nand-addr-offset = <21>; /* ale */
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atmel,nand-cmd-offset = <22>; /* cle */
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nand-on-flash-bbt;
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nand-ecc-mode = "hw";
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atmel,has-pmecc; /* enable PMECC */
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atmel,pmecc-cap = <2>;
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atmel,pmecc-sector-size = <512>;
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atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
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gpios = <&pioD 5 0 /* rdy */
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&pioD 4 0 /* nce */
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0 /* cd */
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>;
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partition@0 {
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...
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};
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};
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/* for NFC supported chips */
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nand0: nand@40000000 {
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compatible = "atmel,at91rm9200-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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...
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nfc@70000000 {
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compatible = "atmel,sama5d3-nfc";
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&hsmc_clk>
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reg = <
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0x70000000 0x10000000 /* NFC Command Registers */
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0xffffc000 0x00000070 /* NFC HSMC regs */
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0x00200000 0x00100000 /* NFC SRAM banks */
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>;
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};
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};
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