forked from Minki/linux
f56a1b24f5
We've been moving all omap2+ based systems to boot in device tree only mode for a few years now. Only omap3 has legacy booting support remaining. Most omap3 boards already have related arch/arm/boot/*.dts* files for booting with device tree. As it seems this board only has minimal support upstreamed for the legacy booting and has not seen activity for on the mailing lists for a few years, let's attempt to remove the related legacy board-*.c file. I do not have this board, but it seems getting the same level of support with device tree based booting is mostly just configuring the .dts file. And there is no need to upgrade the boot loader as we can boot with appended DTB too. And most of the omap3 boards seem to be related to omap3-evm, and omap3beagleboard that are supported with device tree based booting. If somebody is using this board actively with the mainline kernel, please communicate this to the linux-omap mailing list so we can get the board booting with device tree based support. I can help some too getting the minimal device tree based booting going if help is needed. The reason for attempting to remove this board now is that I'd rather get the remaining omap3 legacy booting support into a known state where we at least have a .dts file being written for the remaining legacy boards. That is because for the next few merge cycles we can still revert this patch if absolutely necessary, but I'd rather not get suprised by missing .dts files at the point where we are ready to drop all remaining omap3 legacy booting support later on. http://www.embest-tech.com/product/single-board-computers/index.html Cc: Thomas Weber <thomas@tomweber.eu> Signed-off-by: Tony Lindgren <tony@atomide.com>
295 lines
6.9 KiB
Plaintext
295 lines
6.9 KiB
Plaintext
menu "TI OMAP/AM/DM/DRA Family"
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depends on ARCH_MULTI_V6 || ARCH_MULTI_V7
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config ARCH_OMAP2
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bool "TI OMAP2"
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depends on ARCH_MULTI_V6
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select ARCH_OMAP2PLUS
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select CPU_V6
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select SOC_HAS_OMAP2_SDRC
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config ARCH_OMAP3
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bool "TI OMAP3"
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depends on ARCH_MULTI_V7
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select ARCH_OMAP2PLUS
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select ARM_CPU_SUSPEND if PM
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select OMAP_INTERCONNECT
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select PM_OPP if PM
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select PM if CPU_IDLE
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select SOC_HAS_OMAP2_SDRC
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config ARCH_OMAP4
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bool "TI OMAP4"
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depends on ARCH_MULTI_V7
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select ARCH_OMAP2PLUS
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select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
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select ARM_CPU_SUSPEND if PM
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select ARM_ERRATA_720789
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select ARM_GIC
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select HAVE_ARM_SCU if SMP
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select HAVE_ARM_TWD if SMP
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select OMAP_INTERCONNECT
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select PL310_ERRATA_588369 if CACHE_L2X0
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select PL310_ERRATA_727915 if CACHE_L2X0
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select PM_OPP if PM
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select PM if CPU_IDLE
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select ARM_ERRATA_754322
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select ARM_ERRATA_775420
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config SOC_OMAP5
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bool "TI OMAP5"
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depends on ARCH_MULTI_V7
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select ARCH_OMAP2PLUS
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select ARM_CPU_SUSPEND if PM
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select ARM_GIC
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select HAVE_ARM_SCU if SMP
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select HAVE_ARM_TWD if SMP
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select HAVE_ARM_ARCH_TIMER
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select ARM_ERRATA_798181 if SMP
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config SOC_AM33XX
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bool "TI AM33XX"
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depends on ARCH_MULTI_V7
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select ARCH_OMAP2PLUS
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select ARM_CPU_SUSPEND if PM
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config SOC_AM43XX
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bool "TI AM43x"
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depends on ARCH_MULTI_V7
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select ARCH_OMAP2PLUS
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select ARM_GIC
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select MACH_OMAP_GENERIC
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select MIGHT_HAVE_CACHE_L2X0
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config SOC_DRA7XX
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bool "TI DRA7XX"
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depends on ARCH_MULTI_V7
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select ARCH_OMAP2PLUS
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select ARM_CPU_SUSPEND if PM
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select ARM_GIC
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select HAVE_ARM_ARCH_TIMER
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select IRQ_CROSSBAR
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config ARCH_OMAP2PLUS
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bool
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select ARCH_HAS_BANDGAP
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select ARCH_HAS_HOLES_MEMORYMODEL
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select ARCH_OMAP
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select ARCH_REQUIRE_GPIOLIB
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select CLKSRC_MMIO
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select GENERIC_IRQ_CHIP
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select MACH_OMAP_GENERIC
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select MEMORY
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select OMAP_DM_TIMER
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select OMAP_GPMC
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select PINCTRL
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select SOC_BUS
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select TI_PRIV_EDMA
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select OMAP_IRQCHIP
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help
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Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
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if ARCH_OMAP2PLUS
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menu "TI OMAP2/3/4 Specific Features"
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config ARCH_OMAP2PLUS_TYPICAL
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bool "Typical OMAP configuration"
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default y
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select AEABI
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select HIGHMEM
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select I2C
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select I2C_OMAP
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select MENELAUS if ARCH_OMAP2
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select NEON if CPU_V7
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select PM
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select REGULATOR
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select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
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select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
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select VFP
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help
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Compile a kernel suitable for booting most boards
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config SOC_HAS_OMAP2_SDRC
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bool "OMAP2 SDRAM Controller support"
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config SOC_HAS_REALTIME_COUNTER
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bool "Real time free running counter"
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depends on SOC_OMAP5 || SOC_DRA7XX
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default y
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comment "OMAP Core Type"
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depends on ARCH_OMAP2
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config SOC_OMAP2420
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bool "OMAP2420 support"
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depends on ARCH_OMAP2
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default y
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select OMAP_DM_TIMER
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select SOC_HAS_OMAP2_SDRC
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config SOC_OMAP2430
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bool "OMAP2430 support"
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depends on ARCH_OMAP2
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default y
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select SOC_HAS_OMAP2_SDRC
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config SOC_OMAP3430
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bool "OMAP3430 support"
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depends on ARCH_OMAP3
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default y
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select SOC_HAS_OMAP2_SDRC
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config SOC_TI81XX
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bool "TI81XX support"
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depends on ARCH_OMAP3
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default y
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config OMAP_PACKAGE_CBC
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bool
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config OMAP_PACKAGE_CBB
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bool
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config OMAP_PACKAGE_CUS
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bool
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config OMAP_PACKAGE_CBP
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bool
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comment "OMAP Legacy Platform Data Board Type"
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depends on ARCH_OMAP2PLUS
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config MACH_OMAP_GENERIC
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bool
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config MACH_OMAP2_TUSB6010
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bool
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depends on ARCH_OMAP2 && SOC_OMAP2420
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default y if MACH_NOKIA_N8X0
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config MACH_OMAP3_BEAGLE
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bool "OMAP3 BEAGLE board"
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depends on ARCH_OMAP3
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default y
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select OMAP_PACKAGE_CBB
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config MACH_OMAP_LDP
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bool "OMAP3 LDP board"
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depends on ARCH_OMAP3
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default y
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select OMAP_PACKAGE_CBB
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config MACH_OMAP3530_LV_SOM
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bool "OMAP3 Logic 3530 LV SOM board"
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depends on ARCH_OMAP3
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default y
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select OMAP_PACKAGE_CBB
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help
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Support for the LogicPD OMAP3530 SOM Development kit
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for full description please see the products webpage at
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http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap35x-development-kit
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config MACH_OMAP3_TORPEDO
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bool "OMAP3 Logic 35x Torpedo board"
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depends on ARCH_OMAP3
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default y
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select OMAP_PACKAGE_CBB
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help
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Support for the LogicPD OMAP35x Torpedo Development kit
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for full description please see the products webpage at
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http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit
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config MACH_OVERO
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bool "Gumstix Overo board"
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depends on ARCH_OMAP3
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default y
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select OMAP_PACKAGE_CBB
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config MACH_OMAP3517EVM
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bool "OMAP3517/ AM3517 EVM board"
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depends on ARCH_OMAP3
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default y
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config MACH_OMAP3_PANDORA
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bool "OMAP3 Pandora"
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depends on ARCH_OMAP3
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default y
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select OMAP_PACKAGE_CBB
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select REGULATOR_FIXED_VOLTAGE if REGULATOR
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config MACH_TOUCHBOOK
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bool "OMAP3 Touch Book"
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depends on ARCH_OMAP3
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default y
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select OMAP_PACKAGE_CBB
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config MACH_NOKIA_N810
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bool
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config MACH_NOKIA_N810_WIMAX
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bool
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config MACH_NOKIA_N8X0
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bool "Nokia N800/N810"
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depends on SOC_OMAP2420
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default y
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select MACH_NOKIA_N810
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select MACH_NOKIA_N810_WIMAX
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config MACH_NOKIA_RX51
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bool "Nokia N900 (RX-51) phone"
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depends on ARCH_OMAP3
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default y
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select OMAP_PACKAGE_CBB
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config MACH_CM_T35
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bool "CompuLab CM-T35/CM-T3730 modules"
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depends on ARCH_OMAP3
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default y
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select MACH_CM_T3730
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select OMAP_PACKAGE_CUS
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config MACH_CM_T3730
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bool
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config OMAP3_SDRC_AC_TIMING
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bool "Enable SDRC AC timing register changes"
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depends on ARCH_OMAP3
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default n
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help
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If you know that none of your system initiators will attempt to
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access SDRAM during CORE DVFS, select Y here. This should boost
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SDRAM performance at lower CORE OPPs. There are relatively few
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users who will wish to say yes at this point - almost everyone will
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wish to say no. Selecting yes without understanding what is
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going on could result in system crashes;
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config OMAP4_ERRATA_I688
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bool "OMAP4 errata: Async Bridge Corruption"
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depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM
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select ARCH_HAS_BARRIERS
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help
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If a data is stalled inside asynchronous bridge because of back
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pressure, it may be accepted multiple times, creating pointer
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misalignment that will corrupt next transfers on that data path
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until next reset of the system (No recovery procedure once the
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issue is hit, the path remains consistently broken). Async bridge
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can be found on path between MPU to EMIF and MPU to L3 interconnect.
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This situation can happen only when the idle is initiated by a
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Master Request Disconnection (which is trigged by software when
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executing WFI on CPU).
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The work-around for this errata needs all the initiators connected
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through async bridge must ensure that data path is properly drained
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before issuing WFI. This condition will be met if one Strongly ordered
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access is performed to the target right before executing the WFI.
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In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
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IO barrier ensure that there is no synchronisation loss on initiators
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operating on both interconnect port simultaneously.
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endmenu
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endif
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endmenu
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