forked from Minki/linux
f469cde20a
As of commit 9a1091ef00 ("irqchip: gic: Support hierarchy irq
domain."), Marzen legacy hangs during boot with:
Image Name: 'Linux-3.19.0-rc4'
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 3445880 Bytes = 3.3 MiB
Load Address: 60008000
Entry Point: 60008000
Verifying Checksum ... OK
Loading Kernel Image ... OK
OK
Starting kernel ...
Enabling DEBUG_LL does not seem to change the situation, however this
patch by itself fixes this issue and re-enables normal boot.
This issue happens because the IRQ numbers of the GIC are now virtual,
and no longer match the hardcoded hardware IRQ numbers in the platform
board code.
To fix this, instantiate the GIC from platform board code when compiling
a legacy kernel, like is done for the sh73a0, r8a7740 and r8a7778 legacy code.
Follows same style as the r8a7740 legacy GIC fix by Geert Uytterhoeven,
thanks to him for the initial work.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
781 lines
21 KiB
C
781 lines
21 KiB
C
/*
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* r8a7779 processor support
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*
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* Copyright (C) 2011, 2013 Renesas Solutions Corp.
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* Copyright (C) 2011 Magnus Damm
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* Copyright (C) 2013 Cogent Embedded, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/of_platform.h>
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#include <linux/platform_data/dma-rcar-hpbdma.h>
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#include <linux/platform_data/gpio-rcar.h>
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#include <linux/platform_data/irq-renesas-intc-irqpin.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/input.h>
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#include <linux/io.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_timer.h>
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#include <linux/dma-mapping.h>
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#include <linux/usb/otg.h>
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#include <linux/usb/hcd.h>
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#include <linux/usb/ehci_pdriver.h>
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#include <linux/usb/ohci_pdriver.h>
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#include <linux/pm_runtime.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <asm/mach/map.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "common.h"
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#include "irqs.h"
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#include "r8a7779.h"
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static struct map_desc r8a7779_io_desc[] __initdata = {
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/* 2M entity map for 0xf0000000 (MPCORE) */
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{
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.virtual = 0xf0000000,
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.pfn = __phys_to_pfn(0xf0000000),
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.length = SZ_2M,
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.type = MT_DEVICE_NONSHARED
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},
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/* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
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{
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.virtual = 0xfe000000,
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.pfn = __phys_to_pfn(0xfe000000),
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.length = SZ_16M,
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.type = MT_DEVICE_NONSHARED
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},
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};
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void __init r8a7779_map_io(void)
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{
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debug_ll_io_init();
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iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
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}
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/* IRQ */
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#define INT2SMSKCR0 IOMEM(0xfe7822a0)
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#define INT2SMSKCR1 IOMEM(0xfe7822a4)
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#define INT2SMSKCR2 IOMEM(0xfe7822a8)
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#define INT2SMSKCR3 IOMEM(0xfe7822ac)
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#define INT2SMSKCR4 IOMEM(0xfe7822b0)
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#define INT2NTSR0 IOMEM(0xfe700060)
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#define INT2NTSR1 IOMEM(0xfe700064)
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static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = {
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.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
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.sense_bitfield_width = 2,
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};
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static struct resource irqpin0_resources[] __initdata = {
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DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
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DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
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DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
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DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
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DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
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DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
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DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
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DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
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DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
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};
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void __init r8a7779_init_irq_extpin_dt(int irlm)
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{
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void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
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u32 tmp;
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if (!icr0) {
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pr_warn("r8a7779: unable to setup external irq pin mode\n");
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return;
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}
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tmp = ioread32(icr0);
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if (irlm)
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tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
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else
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tmp &= ~(1 << 23); /* IRL mode - not supported */
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tmp |= (1 << 21); /* LVLMODE = 1 */
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iowrite32(tmp, icr0);
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iounmap(icr0);
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}
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void __init r8a7779_init_irq_extpin(int irlm)
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{
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r8a7779_init_irq_extpin_dt(irlm);
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if (irlm)
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platform_device_register_resndata(
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NULL, "renesas_intc_irqpin", -1,
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irqpin0_resources, ARRAY_SIZE(irqpin0_resources),
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&irqpin0_platform_data, sizeof(irqpin0_platform_data));
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}
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/* PFC/GPIO */
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static struct resource r8a7779_pfc_resources[] = {
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DEFINE_RES_MEM(0xfffc0000, 0x023c),
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};
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static struct platform_device r8a7779_pfc_device = {
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.name = "pfc-r8a7779",
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.id = -1,
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.resource = r8a7779_pfc_resources,
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.num_resources = ARRAY_SIZE(r8a7779_pfc_resources),
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};
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#define R8A7779_GPIO(idx, npins) \
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static struct resource r8a7779_gpio##idx##_resources[] = { \
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DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c), \
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DEFINE_RES_IRQ(gic_iid(0xad + (idx))), \
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}; \
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\
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static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \
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.gpio_base = 32 * (idx), \
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.irq_base = 0, \
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.number_of_pins = npins, \
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.pctl_name = "pfc-r8a7779", \
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}; \
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\
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static struct platform_device r8a7779_gpio##idx##_device = { \
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.name = "gpio_rcar", \
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.id = idx, \
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.resource = r8a7779_gpio##idx##_resources, \
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.num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \
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.dev = { \
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.platform_data = &r8a7779_gpio##idx##_platform_data, \
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}, \
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}
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R8A7779_GPIO(0, 32);
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R8A7779_GPIO(1, 32);
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R8A7779_GPIO(2, 32);
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R8A7779_GPIO(3, 32);
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R8A7779_GPIO(4, 32);
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R8A7779_GPIO(5, 32);
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R8A7779_GPIO(6, 9);
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static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
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&r8a7779_pfc_device,
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&r8a7779_gpio0_device,
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&r8a7779_gpio1_device,
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&r8a7779_gpio2_device,
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&r8a7779_gpio3_device,
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&r8a7779_gpio4_device,
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&r8a7779_gpio5_device,
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&r8a7779_gpio6_device,
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};
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void __init r8a7779_pinmux_init(void)
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{
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platform_add_devices(r8a7779_pinctrl_devices,
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ARRAY_SIZE(r8a7779_pinctrl_devices));
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}
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/* SCIF */
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#define R8A7779_SCIF(index, baseaddr, irq) \
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static struct plat_sci_port scif##index##_platform_data = { \
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.type = PORT_SCIF, \
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
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}; \
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\
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static struct resource scif##index##_resources[] = { \
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DEFINE_RES_MEM(baseaddr, 0x100), \
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DEFINE_RES_IRQ(irq), \
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}; \
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\
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static struct platform_device scif##index##_device = { \
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.name = "sh-sci", \
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.id = index, \
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.resource = scif##index##_resources, \
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.num_resources = ARRAY_SIZE(scif##index##_resources), \
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.dev = { \
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.platform_data = &scif##index##_platform_data, \
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}, \
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}
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R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78));
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R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79));
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R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a));
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R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b));
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R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c));
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R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d));
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/* TMU */
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static struct sh_timer_config tmu0_platform_data = {
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.channels_mask = 7,
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};
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static struct resource tmu0_resources[] = {
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DEFINE_RES_MEM(0xffd80000, 0x30),
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DEFINE_RES_IRQ(gic_iid(0x40)),
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DEFINE_RES_IRQ(gic_iid(0x41)),
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DEFINE_RES_IRQ(gic_iid(0x42)),
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};
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static struct platform_device tmu0_device = {
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.name = "sh-tmu",
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.id = 0,
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.dev = {
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.platform_data = &tmu0_platform_data,
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},
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.resource = tmu0_resources,
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.num_resources = ARRAY_SIZE(tmu0_resources),
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};
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/* I2C */
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static struct resource rcar_i2c0_res[] = {
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{
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.start = 0xffc70000,
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.end = 0xffc70fff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = gic_iid(0x6f),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device i2c0_device = {
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.name = "i2c-rcar",
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.id = 0,
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.resource = rcar_i2c0_res,
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.num_resources = ARRAY_SIZE(rcar_i2c0_res),
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};
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static struct resource rcar_i2c1_res[] = {
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{
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.start = 0xffc71000,
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.end = 0xffc71fff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = gic_iid(0x72),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device i2c1_device = {
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.name = "i2c-rcar",
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.id = 1,
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.resource = rcar_i2c1_res,
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.num_resources = ARRAY_SIZE(rcar_i2c1_res),
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};
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static struct resource rcar_i2c2_res[] = {
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{
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.start = 0xffc72000,
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.end = 0xffc72fff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = gic_iid(0x70),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device i2c2_device = {
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.name = "i2c-rcar",
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.id = 2,
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.resource = rcar_i2c2_res,
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.num_resources = ARRAY_SIZE(rcar_i2c2_res),
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};
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static struct resource rcar_i2c3_res[] = {
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{
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.start = 0xffc73000,
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.end = 0xffc73fff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = gic_iid(0x71),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device i2c3_device = {
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.name = "i2c-rcar",
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.id = 3,
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.resource = rcar_i2c3_res,
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.num_resources = ARRAY_SIZE(rcar_i2c3_res),
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};
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static struct resource sata_resources[] = {
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[0] = {
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.name = "rcar-sata",
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.start = 0xfc600000,
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.end = 0xfc601fff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = gic_iid(0x84),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device sata_device = {
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.name = "sata_rcar",
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.id = -1,
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.resource = sata_resources,
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.num_resources = ARRAY_SIZE(sata_resources),
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.dev = {
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.dma_mask = &sata_device.dev.coherent_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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/* USB */
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static struct usb_phy *phy;
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static int usb_power_on(struct platform_device *pdev)
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{
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if (IS_ERR(phy))
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return PTR_ERR(phy);
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pm_runtime_enable(&pdev->dev);
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pm_runtime_get_sync(&pdev->dev);
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usb_phy_init(phy);
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return 0;
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}
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static void usb_power_off(struct platform_device *pdev)
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{
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if (IS_ERR(phy))
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return;
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usb_phy_shutdown(phy);
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pm_runtime_put_sync(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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}
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static int ehci_init_internal_buffer(struct usb_hcd *hcd)
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{
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/*
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* Below are recommended values from the datasheet;
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* see [USB :: Setting of EHCI Internal Buffer].
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*/
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/* EHCI IP internal buffer setting */
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iowrite32(0x00ff0040, hcd->regs + 0x0094);
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/* EHCI IP internal buffer enable */
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iowrite32(0x00000001, hcd->regs + 0x009C);
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return 0;
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}
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static struct usb_ehci_pdata ehcix_pdata = {
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.power_on = usb_power_on,
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.power_off = usb_power_off,
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.power_suspend = usb_power_off,
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.pre_setup = ehci_init_internal_buffer,
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};
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static struct resource ehci0_resources[] = {
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[0] = {
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.start = 0xffe70000,
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.end = 0xffe70400 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = gic_iid(0x4c),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device ehci0_device = {
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.name = "ehci-platform",
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.id = 0,
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.dev = {
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.dma_mask = &ehci0_device.dev.coherent_dma_mask,
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.coherent_dma_mask = 0xffffffff,
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.platform_data = &ehcix_pdata,
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},
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.num_resources = ARRAY_SIZE(ehci0_resources),
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.resource = ehci0_resources,
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};
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static struct resource ehci1_resources[] = {
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[0] = {
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.start = 0xfff70000,
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.end = 0xfff70400 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = gic_iid(0x4d),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device ehci1_device = {
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.name = "ehci-platform",
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.id = 1,
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.dev = {
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.dma_mask = &ehci1_device.dev.coherent_dma_mask,
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.coherent_dma_mask = 0xffffffff,
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.platform_data = &ehcix_pdata,
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},
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.num_resources = ARRAY_SIZE(ehci1_resources),
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.resource = ehci1_resources,
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};
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static struct usb_ohci_pdata ohcix_pdata = {
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.power_on = usb_power_on,
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.power_off = usb_power_off,
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.power_suspend = usb_power_off,
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};
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static struct resource ohci0_resources[] = {
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[0] = {
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.start = 0xffe70400,
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.end = 0xffe70800 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = gic_iid(0x4c),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device ohci0_device = {
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.name = "ohci-platform",
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.id = 0,
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.dev = {
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.dma_mask = &ohci0_device.dev.coherent_dma_mask,
|
|
.coherent_dma_mask = 0xffffffff,
|
|
.platform_data = &ohcix_pdata,
|
|
},
|
|
.num_resources = ARRAY_SIZE(ohci0_resources),
|
|
.resource = ohci0_resources,
|
|
};
|
|
|
|
static struct resource ohci1_resources[] = {
|
|
[0] = {
|
|
.start = 0xfff70400,
|
|
.end = 0xfff70800 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = gic_iid(0x4d),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device ohci1_device = {
|
|
.name = "ohci-platform",
|
|
.id = 1,
|
|
.dev = {
|
|
.dma_mask = &ohci1_device.dev.coherent_dma_mask,
|
|
.coherent_dma_mask = 0xffffffff,
|
|
.platform_data = &ohcix_pdata,
|
|
},
|
|
.num_resources = ARRAY_SIZE(ohci1_resources),
|
|
.resource = ohci1_resources,
|
|
};
|
|
|
|
/* HPB-DMA */
|
|
|
|
/* Asynchronous mode register bits */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD43_MASK BIT(23) /* MMC1 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE BIT(23) /* MMC1 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD43_MULTI 0 /* MMC1 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK BIT(22) /* MMC1 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST BIT(22) /* MMC1 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST 0 /* MMC1 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD24_MASK BIT(21) /* MMC0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE BIT(21) /* MMC0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD24_MULTI 0 /* MMC0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK BIT(20) /* MMC0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST BIT(20) /* MMC0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST 0 /* MMC0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD41_MASK BIT(19) /* SDHI3 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE BIT(19) /* SDHI3 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD41_MULTI 0 /* SDHI3 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK BIT(18) /* SDHI3 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST BIT(18) /* SDHI3 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST 0 /* SDHI3 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD40_MASK BIT(17) /* SDHI3 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE BIT(17) /* SDHI3 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD40_MULTI 0 /* SDHI3 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK BIT(16) /* SDHI3 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST BIT(16) /* SDHI3 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST 0 /* SDHI3 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD39_MASK BIT(15) /* SDHI3 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE BIT(15) /* SDHI3 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD39_MULTI 0 /* SDHI3 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK BIT(14) /* SDHI3 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST BIT(14) /* SDHI3 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST 0 /* SDHI3 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD27_MASK BIT(13) /* SDHI2 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE BIT(13) /* SDHI2 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD27_MULTI 0 /* SDHI2 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK BIT(12) /* SDHI2 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST BIT(12) /* SDHI2 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST 0 /* SDHI2 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD26_MASK BIT(11) /* SDHI2 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE BIT(11) /* SDHI2 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD26_MULTI 0 /* SDHI2 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK BIT(10) /* SDHI2 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST BIT(10) /* SDHI2 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST 0 /* SDHI2 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD25_MASK BIT(9) /* SDHI2 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE BIT(9) /* SDHI2 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD25_MULTI 0 /* SDHI2 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK BIT(8) /* SDHI2 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST BIT(8) /* SDHI2 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST 0 /* SDHI2 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD23_MASK BIT(7) /* SDHI0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE BIT(7) /* SDHI0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD23_MULTI 0 /* SDHI0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK BIT(6) /* SDHI0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST BIT(6) /* SDHI0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST 0 /* SDHI0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(5) /* SDHI0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(5) /* SDHI0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK BIT(4) /* SDHI0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST BIT(4) /* SDHI0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST 0 /* SDHI0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(3) /* SDHI0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(3) /* SDHI0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK BIT(2) /* SDHI0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST BIT(2) /* SDHI0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST 0 /* SDHI0 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD20_MASK BIT(1) /* SDHI1 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE BIT(1) /* SDHI1 */
|
|
#define HPB_DMAE_ASYNCMDR_ASMD20_MULTI 0 /* SDHI1 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK BIT(0) /* SDHI1 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST BIT(0) /* SDHI1 */
|
|
#define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST 0 /* SDHI1 */
|
|
|
|
static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
|
|
{
|
|
.id = HPBDMA_SLAVE_SDHI0_TX,
|
|
.addr = 0xffe4c000 + 0x30,
|
|
.dcr = HPB_DMAE_DCR_SPDS_16BIT |
|
|
HPB_DMAE_DCR_DMDL |
|
|
HPB_DMAE_DCR_DPDS_16BIT,
|
|
.rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
|
|
HPB_DMAE_ASYNCRSTR_ASRST22 |
|
|
HPB_DMAE_ASYNCRSTR_ASRST23,
|
|
.mdr = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE |
|
|
HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST,
|
|
.mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK |
|
|
HPB_DMAE_ASYNCMDR_ASBTMD21_MASK,
|
|
.port = 0x0D0C,
|
|
.flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
|
|
.dma_ch = 21,
|
|
}, {
|
|
.id = HPBDMA_SLAVE_SDHI0_RX,
|
|
.addr = 0xffe4c000 + 0x30,
|
|
.dcr = HPB_DMAE_DCR_SMDL |
|
|
HPB_DMAE_DCR_SPDS_16BIT |
|
|
HPB_DMAE_DCR_DPDS_16BIT,
|
|
.rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
|
|
HPB_DMAE_ASYNCRSTR_ASRST22 |
|
|
HPB_DMAE_ASYNCRSTR_ASRST23,
|
|
.mdr = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE |
|
|
HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST,
|
|
.mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK |
|
|
HPB_DMAE_ASYNCMDR_ASBTMD22_MASK,
|
|
.port = 0x0D0C,
|
|
.flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
|
|
.dma_ch = 22,
|
|
},
|
|
};
|
|
|
|
static const struct hpb_dmae_channel hpb_dmae_channels[] = {
|
|
HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
|
|
HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
|
|
};
|
|
|
|
static struct hpb_dmae_pdata dma_platform_data __initdata = {
|
|
.slaves = hpb_dmae_slaves,
|
|
.num_slaves = ARRAY_SIZE(hpb_dmae_slaves),
|
|
.channels = hpb_dmae_channels,
|
|
.num_channels = ARRAY_SIZE(hpb_dmae_channels),
|
|
.ts_shift = {
|
|
[XMIT_SZ_8BIT] = 0,
|
|
[XMIT_SZ_16BIT] = 1,
|
|
[XMIT_SZ_32BIT] = 2,
|
|
},
|
|
.num_hw_channels = 44,
|
|
};
|
|
|
|
static struct resource hpb_dmae_resources[] __initdata = {
|
|
/* Channel registers */
|
|
DEFINE_RES_MEM(0xffc08000, 0x1000),
|
|
/* Common registers */
|
|
DEFINE_RES_MEM(0xffc09000, 0x170),
|
|
/* Asynchronous reset registers */
|
|
DEFINE_RES_MEM(0xffc00300, 4),
|
|
/* Asynchronous mode registers */
|
|
DEFINE_RES_MEM(0xffc00400, 4),
|
|
/* IRQ for DMA channels */
|
|
DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ),
|
|
};
|
|
|
|
static void __init r8a7779_register_hpb_dmae(void)
|
|
{
|
|
platform_device_register_resndata(NULL, "hpb-dma-engine",
|
|
-1, hpb_dmae_resources,
|
|
ARRAY_SIZE(hpb_dmae_resources),
|
|
&dma_platform_data,
|
|
sizeof(dma_platform_data));
|
|
}
|
|
|
|
static struct platform_device *r8a7779_early_devices[] __initdata = {
|
|
&tmu0_device,
|
|
};
|
|
|
|
static struct platform_device *r8a7779_standard_devices[] __initdata = {
|
|
&scif0_device,
|
|
&scif1_device,
|
|
&scif2_device,
|
|
&scif3_device,
|
|
&scif4_device,
|
|
&scif5_device,
|
|
&i2c0_device,
|
|
&i2c1_device,
|
|
&i2c2_device,
|
|
&i2c3_device,
|
|
&sata_device,
|
|
};
|
|
|
|
void __init r8a7779_add_standard_devices(void)
|
|
{
|
|
#ifdef CONFIG_CACHE_L2X0
|
|
/* Shared attribute override enable, 64K*16way */
|
|
l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
|
|
#endif
|
|
r8a7779_pm_init();
|
|
|
|
r8a7779_init_pm_domains();
|
|
|
|
platform_add_devices(r8a7779_early_devices,
|
|
ARRAY_SIZE(r8a7779_early_devices));
|
|
platform_add_devices(r8a7779_standard_devices,
|
|
ARRAY_SIZE(r8a7779_standard_devices));
|
|
r8a7779_register_hpb_dmae();
|
|
}
|
|
|
|
void __init r8a7779_add_early_devices(void)
|
|
{
|
|
early_platform_add_devices(r8a7779_early_devices,
|
|
ARRAY_SIZE(r8a7779_early_devices));
|
|
|
|
/* Early serial console setup is not included here due to
|
|
* memory map collisions. The SCIF serial ports in r8a7779
|
|
* are difficult to entity map 1:1 due to collision with the
|
|
* virtual memory range used by the coherent DMA code on ARM.
|
|
*
|
|
* Anyone wanting to debug early can remove UPF_IOREMAP from
|
|
* the sh-sci serial console platform data, adjust mapbase
|
|
* to a static M:N virt:phys mapping that needs to be added to
|
|
* the mappings passed with iotable_init() above.
|
|
*
|
|
* Then add a call to shmobile_setup_console() from this function.
|
|
*
|
|
* As a final step pass earlyprint=sh-sci.2,115200 on the kernel
|
|
* command line in case of the marzen board.
|
|
*/
|
|
}
|
|
|
|
static struct platform_device *r8a7779_late_devices[] __initdata = {
|
|
&ehci0_device,
|
|
&ehci1_device,
|
|
&ohci0_device,
|
|
&ohci1_device,
|
|
};
|
|
|
|
void __init r8a7779_init_late(void)
|
|
{
|
|
/* get USB PHY */
|
|
phy = usb_get_phy(USB_PHY_TYPE_USB2);
|
|
|
|
shmobile_init_late();
|
|
platform_add_devices(r8a7779_late_devices,
|
|
ARRAY_SIZE(r8a7779_late_devices));
|
|
}
|
|
|
|
#ifdef CONFIG_USE_OF
|
|
static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
|
|
{
|
|
return 0; /* always allow wakeup */
|
|
}
|
|
|
|
void __init r8a7779_init_irq_dt(void)
|
|
{
|
|
#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
|
|
void __iomem *gic_dist_base = ioremap_nocache(0xf0001000, 0x1000);
|
|
void __iomem *gic_cpu_base = ioremap_nocache(0xf0000100, 0x1000);
|
|
#endif
|
|
gic_arch_extn.irq_set_wake = r8a7779_set_wake;
|
|
|
|
#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
|
|
gic_init(0, 29, gic_dist_base, gic_cpu_base);
|
|
#else
|
|
irqchip_init();
|
|
#endif
|
|
/* route all interrupts to ARM */
|
|
__raw_writel(0xffffffff, INT2NTSR0);
|
|
__raw_writel(0x3fffffff, INT2NTSR1);
|
|
|
|
/* unmask all known interrupts in INTCS2 */
|
|
__raw_writel(0xfffffff0, INT2SMSKCR0);
|
|
__raw_writel(0xfff7ffff, INT2SMSKCR1);
|
|
__raw_writel(0xfffbffdf, INT2SMSKCR2);
|
|
__raw_writel(0xbffffffc, INT2SMSKCR3);
|
|
__raw_writel(0x003fee3f, INT2SMSKCR4);
|
|
}
|
|
|
|
#define MODEMR 0xffcc0020
|
|
|
|
u32 __init r8a7779_read_mode_pins(void)
|
|
{
|
|
static u32 mode;
|
|
static bool mode_valid;
|
|
|
|
if (!mode_valid) {
|
|
void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
|
|
BUG_ON(!modemr);
|
|
mode = ioread32(modemr);
|
|
iounmap(modemr);
|
|
mode_valid = true;
|
|
}
|
|
|
|
return mode;
|
|
}
|
|
|
|
static const char *r8a7779_compat_dt[] __initdata = {
|
|
"renesas,r8a7779",
|
|
NULL,
|
|
};
|
|
|
|
DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
|
|
.map_io = r8a7779_map_io,
|
|
.init_early = shmobile_init_delay,
|
|
.init_irq = r8a7779_init_irq_dt,
|
|
.init_late = shmobile_init_late,
|
|
.dt_compat = r8a7779_compat_dt,
|
|
MACHINE_END
|
|
#endif /* CONFIG_USE_OF */
|