Nicholas Piggin f4329f2ecb powerpc/64s: Reduce exception alignment ... Exception handlers are aligned to 128 bytes (L1 cache) on 64s, which is overkill. It can reduce the icache footprint of any individual exception path. However taken as a whole, the expansion in icache footprint seems likely to be counter-productive and cause more total misses. Create IFETCH_ALIGN_SHIFT/BYTES, which should give optimal ifetch alignment with much more reasonable alignment. This saves 1792 bytes from head_64.o text with an allmodconfig build. Other subarchitectures should define appropriate IFETCH_ALIGN_SHIFT values if this becomes more widely used. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>		2016-11-14 11:11:51 +11:00
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asm	powerpc/64s: Reduce exception alignment	2016-11-14 11:11:51 +11:00
uapi/asm	powerpc/ptrace: Enable support for Performance Monitor registers	2016-08-01 11:15:24 +10:00