56ade8fe3f
Add support for new generation Mellanox Spectrum ASIC, 10/25/40/50 and 100Gb/s Ethernet Switch. The initial driver implements bridge forwarding offload including bridge internal VLAN support, FDB static entries, FDB learning and HW ageing including their setup. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Elad Raz <eladr@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
423 lines
12 KiB
C
423 lines
12 KiB
C
/*
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* drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c
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* Copyright (c) 2015 Mellanox Technologies. All rights reserved.
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* Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the names of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include "spectrum.h"
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#include "core.h"
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#include "port.h"
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#include "reg.h"
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struct mlxsw_sp_pb {
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u8 index;
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u16 size;
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};
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#define MLXSW_SP_PB(_index, _size) \
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{ \
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.index = _index, \
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.size = _size, \
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}
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static const struct mlxsw_sp_pb mlxsw_sp_pbs[] = {
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MLXSW_SP_PB(0, 208),
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MLXSW_SP_PB(1, 208),
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MLXSW_SP_PB(2, 208),
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MLXSW_SP_PB(3, 208),
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MLXSW_SP_PB(4, 208),
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MLXSW_SP_PB(5, 208),
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MLXSW_SP_PB(6, 208),
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MLXSW_SP_PB(7, 208),
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MLXSW_SP_PB(9, 208),
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};
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#define MLXSW_SP_PBS_LEN ARRAY_SIZE(mlxsw_sp_pbs)
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static int mlxsw_sp_port_pb_init(struct mlxsw_sp_port *mlxsw_sp_port)
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{
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char pbmc_pl[MLXSW_REG_PBMC_LEN];
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int i;
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mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port,
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0xffff, 0xffff / 2);
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for (i = 0; i < MLXSW_SP_PBS_LEN; i++) {
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const struct mlxsw_sp_pb *pb;
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pb = &mlxsw_sp_pbs[i];
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mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pb->index, pb->size);
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}
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return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core,
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MLXSW_REG(pbmc), pbmc_pl);
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}
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#define MLXSW_SP_SB_BYTES_PER_CELL 96
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struct mlxsw_sp_sb_pool {
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u8 pool;
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enum mlxsw_reg_sbpr_dir dir;
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enum mlxsw_reg_sbpr_mode mode;
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u32 size;
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};
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#define MLXSW_SP_SB_POOL_INGRESS_SIZE \
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((15000000 - (2 * 20000 * MLXSW_PORT_MAX_PORTS)) / \
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MLXSW_SP_SB_BYTES_PER_CELL)
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#define MLXSW_SP_SB_POOL_EGRESS_SIZE \
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((14000000 - (8 * 1500 * MLXSW_PORT_MAX_PORTS)) / \
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MLXSW_SP_SB_BYTES_PER_CELL)
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#define MLXSW_SP_SB_POOL(_pool, _dir, _mode, _size) \
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{ \
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.pool = _pool, \
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.dir = _dir, \
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.mode = _mode, \
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.size = _size, \
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}
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#define MLXSW_SP_SB_POOL_INGRESS(_pool, _size) \
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MLXSW_SP_SB_POOL(_pool, MLXSW_REG_SBPR_DIR_INGRESS, \
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MLXSW_REG_SBPR_MODE_DYNAMIC, _size)
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#define MLXSW_SP_SB_POOL_EGRESS(_pool, _size) \
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MLXSW_SP_SB_POOL(_pool, MLXSW_REG_SBPR_DIR_EGRESS, \
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MLXSW_REG_SBPR_MODE_DYNAMIC, _size)
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static const struct mlxsw_sp_sb_pool mlxsw_sp_sb_pools[] = {
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MLXSW_SP_SB_POOL_INGRESS(0, MLXSW_SP_SB_POOL_INGRESS_SIZE),
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MLXSW_SP_SB_POOL_INGRESS(1, 0),
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MLXSW_SP_SB_POOL_INGRESS(2, 0),
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MLXSW_SP_SB_POOL_INGRESS(3, 0),
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MLXSW_SP_SB_POOL_EGRESS(0, MLXSW_SP_SB_POOL_EGRESS_SIZE),
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MLXSW_SP_SB_POOL_EGRESS(1, 0),
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MLXSW_SP_SB_POOL_EGRESS(2, 0),
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MLXSW_SP_SB_POOL_EGRESS(2, MLXSW_SP_SB_POOL_EGRESS_SIZE),
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};
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#define MLXSW_SP_SB_POOLS_LEN ARRAY_SIZE(mlxsw_sp_sb_pools)
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static int mlxsw_sp_sb_pools_init(struct mlxsw_sp *mlxsw_sp)
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{
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char sbpr_pl[MLXSW_REG_SBPR_LEN];
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int i;
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int err;
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for (i = 0; i < MLXSW_SP_SB_POOLS_LEN; i++) {
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const struct mlxsw_sp_sb_pool *pool;
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pool = &mlxsw_sp_sb_pools[i];
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mlxsw_reg_sbpr_pack(sbpr_pl, pool->pool, pool->dir,
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pool->mode, pool->size);
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err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbpr), sbpr_pl);
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if (err)
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return err;
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}
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return 0;
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}
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struct mlxsw_sp_sb_cm {
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union {
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u8 pg;
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u8 tc;
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} u;
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enum mlxsw_reg_sbcm_dir dir;
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u32 min_buff;
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u32 max_buff;
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u8 pool;
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};
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#define MLXSW_SP_SB_CM(_pg_tc, _dir, _min_buff, _max_buff, _pool) \
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{ \
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.u.pg = _pg_tc, \
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.dir = _dir, \
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.min_buff = _min_buff, \
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.max_buff = _max_buff, \
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.pool = _pool, \
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}
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#define MLXSW_SP_SB_CM_INGRESS(_pg, _min_buff, _max_buff) \
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MLXSW_SP_SB_CM(_pg, MLXSW_REG_SBCM_DIR_INGRESS, \
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_min_buff, _max_buff, 0)
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#define MLXSW_SP_SB_CM_EGRESS(_tc, _min_buff, _max_buff) \
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MLXSW_SP_SB_CM(_tc, MLXSW_REG_SBCM_DIR_EGRESS, \
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_min_buff, _max_buff, 0)
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#define MLXSW_SP_CPU_PORT_SB_CM_EGRESS(_tc) \
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MLXSW_SP_SB_CM(_tc, MLXSW_REG_SBCM_DIR_EGRESS, 104, 2, 3)
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static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms[] = {
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MLXSW_SP_SB_CM_INGRESS(0, 10000 / MLXSW_SP_SB_BYTES_PER_CELL, 8),
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MLXSW_SP_SB_CM_INGRESS(1, 0, 0),
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MLXSW_SP_SB_CM_INGRESS(2, 0, 0),
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MLXSW_SP_SB_CM_INGRESS(3, 0, 0),
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MLXSW_SP_SB_CM_INGRESS(4, 0, 0),
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MLXSW_SP_SB_CM_INGRESS(5, 0, 0),
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MLXSW_SP_SB_CM_INGRESS(6, 0, 0),
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MLXSW_SP_SB_CM_INGRESS(7, 0, 0),
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MLXSW_SP_SB_CM_INGRESS(9, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff),
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MLXSW_SP_SB_CM_EGRESS(0, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
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MLXSW_SP_SB_CM_EGRESS(1, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
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MLXSW_SP_SB_CM_EGRESS(2, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
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MLXSW_SP_SB_CM_EGRESS(3, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
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MLXSW_SP_SB_CM_EGRESS(4, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
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MLXSW_SP_SB_CM_EGRESS(5, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
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MLXSW_SP_SB_CM_EGRESS(6, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
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MLXSW_SP_SB_CM_EGRESS(7, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
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MLXSW_SP_SB_CM_EGRESS(8, 0, 0),
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MLXSW_SP_SB_CM_EGRESS(9, 0, 0),
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MLXSW_SP_SB_CM_EGRESS(10, 0, 0),
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MLXSW_SP_SB_CM_EGRESS(11, 0, 0),
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MLXSW_SP_SB_CM_EGRESS(12, 0, 0),
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MLXSW_SP_SB_CM_EGRESS(13, 0, 0),
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MLXSW_SP_SB_CM_EGRESS(14, 0, 0),
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MLXSW_SP_SB_CM_EGRESS(15, 0, 0),
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MLXSW_SP_SB_CM_EGRESS(16, 1, 0xff),
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};
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#define MLXSW_SP_SB_CMS_LEN ARRAY_SIZE(mlxsw_sp_sb_cms)
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static const struct mlxsw_sp_sb_cm mlxsw_sp_cpu_port_sb_cms[] = {
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(0),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(1),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(2),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(3),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(4),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(5),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(6),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(7),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(8),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(9),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(10),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(11),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(12),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(13),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(14),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(15),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(16),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(17),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(18),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(19),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(20),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(21),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(22),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(23),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(24),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(25),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(26),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(27),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(28),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(29),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(30),
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MLXSW_SP_CPU_PORT_SB_CM_EGRESS(31),
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};
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#define MLXSW_SP_CPU_PORT_SB_MCS_LEN \
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ARRAY_SIZE(mlxsw_sp_cpu_port_sb_cms)
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static int mlxsw_sp_sb_cms_init(struct mlxsw_sp *mlxsw_sp, u8 local_port,
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const struct mlxsw_sp_sb_cm *cms,
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size_t cms_len)
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{
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char sbcm_pl[MLXSW_REG_SBCM_LEN];
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int i;
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int err;
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for (i = 0; i < cms_len; i++) {
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const struct mlxsw_sp_sb_cm *cm;
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cm = &cms[i];
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mlxsw_reg_sbcm_pack(sbcm_pl, local_port, cm->u.pg, cm->dir,
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cm->min_buff, cm->max_buff, cm->pool);
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err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbcm), sbcm_pl);
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if (err)
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return err;
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}
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return 0;
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}
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static int mlxsw_sp_port_sb_cms_init(struct mlxsw_sp_port *mlxsw_sp_port)
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{
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return mlxsw_sp_sb_cms_init(mlxsw_sp_port->mlxsw_sp,
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mlxsw_sp_port->local_port, mlxsw_sp_sb_cms,
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MLXSW_SP_SB_CMS_LEN);
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}
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static int mlxsw_sp_cpu_port_sb_cms_init(struct mlxsw_sp *mlxsw_sp)
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{
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return mlxsw_sp_sb_cms_init(mlxsw_sp, 0, mlxsw_sp_cpu_port_sb_cms,
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MLXSW_SP_CPU_PORT_SB_MCS_LEN);
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}
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struct mlxsw_sp_sb_pm {
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u8 pool;
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enum mlxsw_reg_sbpm_dir dir;
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u32 min_buff;
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u32 max_buff;
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};
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#define MLXSW_SP_SB_PM(_pool, _dir, _min_buff, _max_buff) \
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{ \
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.pool = _pool, \
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.dir = _dir, \
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.min_buff = _min_buff, \
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.max_buff = _max_buff, \
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}
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#define MLXSW_SP_SB_PM_INGRESS(_pool, _min_buff, _max_buff) \
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MLXSW_SP_SB_PM(_pool, MLXSW_REG_SBPM_DIR_INGRESS, \
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_min_buff, _max_buff)
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#define MLXSW_SP_SB_PM_EGRESS(_pool, _min_buff, _max_buff) \
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MLXSW_SP_SB_PM(_pool, MLXSW_REG_SBPM_DIR_EGRESS, \
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_min_buff, _max_buff)
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static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms[] = {
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MLXSW_SP_SB_PM_INGRESS(0, 0, 0xff),
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MLXSW_SP_SB_PM_INGRESS(1, 0, 0),
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MLXSW_SP_SB_PM_INGRESS(2, 0, 0),
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MLXSW_SP_SB_PM_INGRESS(3, 0, 0),
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MLXSW_SP_SB_PM_EGRESS(0, 0, 7),
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MLXSW_SP_SB_PM_EGRESS(1, 0, 0),
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MLXSW_SP_SB_PM_EGRESS(2, 0, 0),
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MLXSW_SP_SB_PM_EGRESS(3, 0, 0),
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};
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#define MLXSW_SP_SB_PMS_LEN ARRAY_SIZE(mlxsw_sp_sb_pms)
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static int mlxsw_sp_port_sb_pms_init(struct mlxsw_sp_port *mlxsw_sp_port)
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{
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char sbpm_pl[MLXSW_REG_SBPM_LEN];
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int i;
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int err;
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for (i = 0; i < MLXSW_SP_SB_PMS_LEN; i++) {
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const struct mlxsw_sp_sb_pm *pm;
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pm = &mlxsw_sp_sb_pms[i];
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mlxsw_reg_sbpm_pack(sbpm_pl, mlxsw_sp_port->local_port,
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pm->pool, pm->dir,
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pm->min_buff, pm->max_buff);
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err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core,
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MLXSW_REG(sbpm), sbpm_pl);
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if (err)
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return err;
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}
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return 0;
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}
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struct mlxsw_sp_sb_mm {
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u8 prio;
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u32 min_buff;
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u32 max_buff;
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u8 pool;
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};
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#define MLXSW_SP_SB_MM(_prio, _min_buff, _max_buff, _pool) \
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{ \
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.prio = _prio, \
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.min_buff = _min_buff, \
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.max_buff = _max_buff, \
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.pool = _pool, \
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}
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static const struct mlxsw_sp_sb_mm mlxsw_sp_sb_mms[] = {
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MLXSW_SP_SB_MM(0, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
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MLXSW_SP_SB_MM(1, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
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MLXSW_SP_SB_MM(2, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
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MLXSW_SP_SB_MM(3, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
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MLXSW_SP_SB_MM(4, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
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MLXSW_SP_SB_MM(5, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
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MLXSW_SP_SB_MM(6, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
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MLXSW_SP_SB_MM(7, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
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MLXSW_SP_SB_MM(8, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
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MLXSW_SP_SB_MM(9, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
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MLXSW_SP_SB_MM(10, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
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MLXSW_SP_SB_MM(11, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
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MLXSW_SP_SB_MM(12, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
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MLXSW_SP_SB_MM(13, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
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MLXSW_SP_SB_MM(14, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
|
|
};
|
|
|
|
#define MLXSW_SP_SB_MMS_LEN ARRAY_SIZE(mlxsw_sp_sb_mms)
|
|
|
|
static int mlxsw_sp_sb_mms_init(struct mlxsw_sp *mlxsw_sp)
|
|
{
|
|
char sbmm_pl[MLXSW_REG_SBMM_LEN];
|
|
int i;
|
|
int err;
|
|
|
|
for (i = 0; i < MLXSW_SP_SB_MMS_LEN; i++) {
|
|
const struct mlxsw_sp_sb_mm *mc;
|
|
|
|
mc = &mlxsw_sp_sb_mms[i];
|
|
mlxsw_reg_sbmm_pack(sbmm_pl, mc->prio, mc->min_buff,
|
|
mc->max_buff, mc->pool);
|
|
err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbmm), sbmm_pl);
|
|
if (err)
|
|
return err;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp)
|
|
{
|
|
int err;
|
|
|
|
err = mlxsw_sp_sb_pools_init(mlxsw_sp);
|
|
if (err)
|
|
return err;
|
|
err = mlxsw_sp_cpu_port_sb_cms_init(mlxsw_sp);
|
|
if (err)
|
|
return err;
|
|
err = mlxsw_sp_sb_mms_init(mlxsw_sp);
|
|
|
|
return err;
|
|
}
|
|
|
|
int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port)
|
|
{
|
|
int err;
|
|
|
|
err = mlxsw_sp_port_pb_init(mlxsw_sp_port);
|
|
if (err)
|
|
return err;
|
|
err = mlxsw_sp_port_sb_cms_init(mlxsw_sp_port);
|
|
if (err)
|
|
return err;
|
|
err = mlxsw_sp_port_sb_pms_init(mlxsw_sp_port);
|
|
|
|
return err;
|
|
}
|