forked from Minki/linux
4f88bd23ba
This adds an interface for configuring Qualcomm's "secure SMMU" and adds support for booting the modem Hexagon on MSM8996. Two new debugfs entries are added in the remoteproc core to introspect the list of memory carveouts and the loaded resource table. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJaD26iAAoJEAsfOT8Nma3FUp0QAL/WZhL8QsvVFbAlv/Aa6NKm z8blXscD0GKdQWDWGaGPtpbnpOWOYhJs9WxstiB2q9ooSa9brIdjG5ukr4DTgtRs 12If5tfkVFIjlBhAdYYK+biNSQtZE+37jb7aJ+j4N3Po3O72pxekcLMLhAdvY6yk zHnhDZ8N7KBxAa0eOg7PJz7AGRF6BHhPxkqgJm0FzBj4HLQ/lwrv6iYJRrZgw6CT OhIHgPwCSHmt2fTO2QDLOWJtbVMSFhunHbuYlzPwvhMAGCT87VmXCIkW8iVhcD24 uJMrFbQoBoWVMB68JgGUKd7SSs8pV7DMrGfJll1kBEQfMLynn8Omre7WDAfwjUEn ACasSDWdWEPABJoIRVkGhS+2BnfCehdvDC7QxFFPAf8oc49O3t6DyXcCQdcVkzzE f1r/G2JKsoNQxjklFJewU5r0EjWgvV/78Dmpi7tuUtjgMSyEqkYORmInbbFIqZrU 9bHCqrmlxuRFSklxoG2u7F2SVYgMVlqM4rmj8QqR85SeIfyZtcCx5i5yAj8dZsI1 JVjucOCROHFqs/3SYFKlo6x4XHIchJD4p64QOXPCVhw7R1NXTPRTFBCQ75PKdiD1 d7kcGhdaz2cMeN1WRhIQ00lh/uiDNd4Ez7sDuU8MnWiEcIs1/ZP1LCHZTNttoljH rWZp4XlrhT+Vx91zV5u5 =lnNj -----END PGP SIGNATURE----- Merge tag 'rproc-v4.15' of git://github.com/andersson/remoteproc Pull remoteproc updates from Bjorn Andersson: "This adds an interface for configuring Qualcomm's "secure SMMU" and adds support for booting the modem Hexagon on MSM8996. Two new debugfs entries are added in the remoteproc core to introspect the list of memory carveouts and the loaded resource table" * tag 'rproc-v4.15' of git://github.com/andersson/remoteproc: remoteproc: qcom: Fix error handling paths in order to avoid memory leaks remoteproc: qcom: Drop pr_err in q6v5_xfer_mem_ownership() remoteproc: debug: add carveouts list dump feature remoteproc: debug: add resource table dump feature remoteproc: qcom: Add support for mss remoteproc on msm8996 remoteproc: qcom: Make secure world call for mem ownership switch remoteproc: qcom: refactor mss fw image loading sequence firmware: scm: Add new SCM call API for switching memory ownership
513 lines
12 KiB
C
513 lines
12 KiB
C
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/mutex.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/qcom_scm.h>
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#include <linux/arm-smccc.h>
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#include <linux/dma-mapping.h>
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#include "qcom_scm.h"
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#define QCOM_SCM_FNID(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF))
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#define MAX_QCOM_SCM_ARGS 10
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#define MAX_QCOM_SCM_RETS 3
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enum qcom_scm_arg_types {
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QCOM_SCM_VAL,
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QCOM_SCM_RO,
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QCOM_SCM_RW,
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QCOM_SCM_BUFVAL,
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};
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#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
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(((a) & 0x3) << 4) | \
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(((b) & 0x3) << 6) | \
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(((c) & 0x3) << 8) | \
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(((d) & 0x3) << 10) | \
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(((e) & 0x3) << 12) | \
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(((f) & 0x3) << 14) | \
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(((g) & 0x3) << 16) | \
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(((h) & 0x3) << 18) | \
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(((i) & 0x3) << 20) | \
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(((j) & 0x3) << 22) | \
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((num) & 0xf))
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#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
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/**
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* struct qcom_scm_desc
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* @arginfo: Metadata describing the arguments in args[]
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* @args: The array of arguments for the secure syscall
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* @res: The values returned by the secure syscall
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*/
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struct qcom_scm_desc {
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u32 arginfo;
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u64 args[MAX_QCOM_SCM_ARGS];
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};
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static u64 qcom_smccc_convention = -1;
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static DEFINE_MUTEX(qcom_scm_lock);
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#define QCOM_SCM_EBUSY_WAIT_MS 30
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#define QCOM_SCM_EBUSY_MAX_RETRY 20
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#define N_EXT_QCOM_SCM_ARGS 7
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#define FIRST_EXT_ARG_IDX 3
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#define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1)
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/**
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* qcom_scm_call() - Invoke a syscall in the secure world
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* @dev: device
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* @svc_id: service identifier
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* @cmd_id: command identifier
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* @desc: Descriptor structure containing arguments and return values
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*
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* Sends a command to the SCM and waits for the command to finish processing.
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* This should *only* be called in pre-emptible context.
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*/
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static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
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const struct qcom_scm_desc *desc,
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struct arm_smccc_res *res)
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{
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int arglen = desc->arginfo & 0xf;
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int retry_count = 0, i;
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u32 fn_id = QCOM_SCM_FNID(svc_id, cmd_id);
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u64 cmd, x5 = desc->args[FIRST_EXT_ARG_IDX];
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dma_addr_t args_phys = 0;
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void *args_virt = NULL;
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size_t alloc_len;
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struct arm_smccc_quirk quirk = {.id = ARM_SMCCC_QUIRK_QCOM_A6};
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if (unlikely(arglen > N_REGISTER_ARGS)) {
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alloc_len = N_EXT_QCOM_SCM_ARGS * sizeof(u64);
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args_virt = kzalloc(PAGE_ALIGN(alloc_len), GFP_KERNEL);
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if (!args_virt)
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return -ENOMEM;
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if (qcom_smccc_convention == ARM_SMCCC_SMC_32) {
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__le32 *args = args_virt;
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for (i = 0; i < N_EXT_QCOM_SCM_ARGS; i++)
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args[i] = cpu_to_le32(desc->args[i +
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FIRST_EXT_ARG_IDX]);
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} else {
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__le64 *args = args_virt;
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for (i = 0; i < N_EXT_QCOM_SCM_ARGS; i++)
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args[i] = cpu_to_le64(desc->args[i +
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FIRST_EXT_ARG_IDX]);
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}
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args_phys = dma_map_single(dev, args_virt, alloc_len,
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DMA_TO_DEVICE);
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if (dma_mapping_error(dev, args_phys)) {
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kfree(args_virt);
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return -ENOMEM;
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}
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x5 = args_phys;
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}
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do {
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mutex_lock(&qcom_scm_lock);
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cmd = ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL,
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qcom_smccc_convention,
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ARM_SMCCC_OWNER_SIP, fn_id);
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quirk.state.a6 = 0;
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do {
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arm_smccc_smc_quirk(cmd, desc->arginfo, desc->args[0],
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desc->args[1], desc->args[2], x5,
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quirk.state.a6, 0, res, &quirk);
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if (res->a0 == QCOM_SCM_INTERRUPTED)
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cmd = res->a0;
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} while (res->a0 == QCOM_SCM_INTERRUPTED);
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mutex_unlock(&qcom_scm_lock);
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if (res->a0 == QCOM_SCM_V2_EBUSY) {
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if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY)
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break;
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msleep(QCOM_SCM_EBUSY_WAIT_MS);
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}
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} while (res->a0 == QCOM_SCM_V2_EBUSY);
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if (args_virt) {
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dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE);
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kfree(args_virt);
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}
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if (res->a0 < 0)
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return qcom_scm_remap_error(res->a0);
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return 0;
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}
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/**
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* qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
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* @entry: Entry point function for the cpus
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* @cpus: The cpumask of cpus that will use the entry point
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*
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* Set the cold boot address of the cpus. Any cpu outside the supported
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* range would be removed from the cpu present mask.
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*/
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int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
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{
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return -ENOTSUPP;
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}
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/**
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* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
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* @dev: Device pointer
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* @entry: Entry point function for the cpus
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* @cpus: The cpumask of cpus that will use the entry point
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*
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* Set the Linux entry point for the SCM to transfer control to when coming
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* out of a power down. CPU power down may be executed on cpuidle or hotplug.
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*/
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int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
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const cpumask_t *cpus)
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{
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return -ENOTSUPP;
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}
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/**
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* qcom_scm_cpu_power_down() - Power down the cpu
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* @flags - Flags to flush cache
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*
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* This is an end point to power down cpu. If there was a pending interrupt,
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* the control would return from this function, otherwise, the cpu jumps to the
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* warm boot entry point set for this cpu upon reset.
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*/
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void __qcom_scm_cpu_power_down(u32 flags)
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{
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}
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int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
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{
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int ret;
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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desc.arginfo = QCOM_SCM_ARGS(1);
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desc.args[0] = QCOM_SCM_FNID(svc_id, cmd_id) |
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(ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD,
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&desc, &res);
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return ret ? : res.a1;
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}
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int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
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u32 req_cnt, u32 *resp)
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{
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int ret;
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
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return -ERANGE;
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desc.args[0] = req[0].addr;
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desc.args[1] = req[0].val;
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desc.args[2] = req[1].addr;
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desc.args[3] = req[1].val;
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desc.args[4] = req[2].addr;
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desc.args[5] = req[2].val;
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desc.args[6] = req[3].addr;
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desc.args[7] = req[3].val;
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desc.args[8] = req[4].addr;
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desc.args[9] = req[4].val;
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desc.arginfo = QCOM_SCM_ARGS(10);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_CMD_HDCP, &desc,
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&res);
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*resp = res.a1;
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return ret;
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}
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void __qcom_scm_init(void)
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{
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u64 cmd;
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struct arm_smccc_res res;
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u32 function = QCOM_SCM_FNID(QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD);
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/* First try a SMC64 call */
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cmd = ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64,
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ARM_SMCCC_OWNER_SIP, function);
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arm_smccc_smc(cmd, QCOM_SCM_ARGS(1), cmd & (~BIT(ARM_SMCCC_TYPE_SHIFT)),
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0, 0, 0, 0, 0, &res);
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if (!res.a0 && res.a1)
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qcom_smccc_convention = ARM_SMCCC_SMC_64;
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else
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qcom_smccc_convention = ARM_SMCCC_SMC_32;
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}
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bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)
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{
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int ret;
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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desc.args[0] = peripheral;
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desc.arginfo = QCOM_SCM_ARGS(1);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
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QCOM_SCM_PAS_IS_SUPPORTED_CMD,
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&desc, &res);
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return ret ? false : !!res.a1;
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}
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int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
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dma_addr_t metadata_phys)
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{
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int ret;
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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desc.args[0] = peripheral;
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desc.args[1] = metadata_phys;
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desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_INIT_IMAGE_CMD,
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&desc, &res);
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return ret ? : res.a1;
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}
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int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
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phys_addr_t addr, phys_addr_t size)
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{
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int ret;
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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desc.args[0] = peripheral;
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desc.args[1] = addr;
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desc.args[2] = size;
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desc.arginfo = QCOM_SCM_ARGS(3);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_MEM_SETUP_CMD,
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&desc, &res);
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return ret ? : res.a1;
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}
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int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)
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{
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int ret;
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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desc.args[0] = peripheral;
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desc.arginfo = QCOM_SCM_ARGS(1);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
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QCOM_SCM_PAS_AUTH_AND_RESET_CMD,
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&desc, &res);
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return ret ? : res.a1;
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}
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int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral)
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{
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int ret;
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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desc.args[0] = peripheral;
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desc.arginfo = QCOM_SCM_ARGS(1);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_SHUTDOWN_CMD,
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&desc, &res);
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return ret ? : res.a1;
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}
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int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
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{
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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int ret;
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desc.args[0] = reset;
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desc.args[1] = 0;
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desc.arginfo = QCOM_SCM_ARGS(2);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_MSS_RESET, &desc,
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&res);
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return ret ? : res.a1;
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}
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int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
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{
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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int ret;
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desc.args[0] = state;
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desc.args[1] = id;
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desc.arginfo = QCOM_SCM_ARGS(2);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_REMOTE_STATE,
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&desc, &res);
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return ret ? : res.a1;
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}
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int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
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size_t mem_sz, phys_addr_t src, size_t src_sz,
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phys_addr_t dest, size_t dest_sz)
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{
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int ret;
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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desc.args[0] = mem_region;
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desc.args[1] = mem_sz;
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desc.args[2] = src;
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desc.args[3] = src_sz;
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desc.args[4] = dest;
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desc.args[5] = dest_sz;
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desc.args[6] = 0;
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desc.arginfo = QCOM_SCM_ARGS(7, QCOM_SCM_RO, QCOM_SCM_VAL,
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QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO,
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QCOM_SCM_VAL, QCOM_SCM_VAL);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP,
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QCOM_MEM_PROT_ASSIGN_ID,
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&desc, &res);
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return ret ? : res.a1;
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}
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int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare)
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{
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struct qcom_scm_desc desc = {0};
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struct arm_smccc_res res;
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int ret;
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desc.args[0] = device_id;
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desc.args[1] = spare;
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desc.arginfo = QCOM_SCM_ARGS(2);
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ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP, QCOM_SCM_RESTORE_SEC_CFG,
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&desc, &res);
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return ret ? : res.a1;
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|
}
|
|
|
|
int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
|
|
size_t *size)
|
|
{
|
|
struct qcom_scm_desc desc = {0};
|
|
struct arm_smccc_res res;
|
|
int ret;
|
|
|
|
desc.args[0] = spare;
|
|
desc.arginfo = QCOM_SCM_ARGS(1);
|
|
|
|
ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP,
|
|
QCOM_SCM_IOMMU_SECURE_PTBL_SIZE, &desc, &res);
|
|
|
|
if (size)
|
|
*size = res.a1;
|
|
|
|
return ret ? : res.a2;
|
|
}
|
|
|
|
int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
|
|
u32 spare)
|
|
{
|
|
struct qcom_scm_desc desc = {0};
|
|
struct arm_smccc_res res;
|
|
int ret;
|
|
|
|
desc.args[0] = addr;
|
|
desc.args[1] = size;
|
|
desc.args[2] = spare;
|
|
desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL,
|
|
QCOM_SCM_VAL);
|
|
|
|
ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP,
|
|
QCOM_SCM_IOMMU_SECURE_PTBL_INIT, &desc, &res);
|
|
|
|
/* the pg table has been initialized already, ignore the error */
|
|
if (ret == -EPERM)
|
|
ret = 0;
|
|
|
|
return ret;
|
|
}
|
|
|
|
int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
|
|
{
|
|
struct qcom_scm_desc desc = {0};
|
|
struct arm_smccc_res res;
|
|
|
|
desc.args[0] = QCOM_SCM_SET_DLOAD_MODE;
|
|
desc.args[1] = enable ? QCOM_SCM_SET_DLOAD_MODE : 0;
|
|
desc.arginfo = QCOM_SCM_ARGS(2);
|
|
|
|
return qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_DLOAD_MODE,
|
|
&desc, &res);
|
|
}
|
|
|
|
int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
|
|
unsigned int *val)
|
|
{
|
|
struct qcom_scm_desc desc = {0};
|
|
struct arm_smccc_res res;
|
|
int ret;
|
|
|
|
desc.args[0] = addr;
|
|
desc.arginfo = QCOM_SCM_ARGS(1);
|
|
|
|
ret = qcom_scm_call(dev, QCOM_SCM_SVC_IO, QCOM_SCM_IO_READ,
|
|
&desc, &res);
|
|
if (ret >= 0)
|
|
*val = res.a1;
|
|
|
|
return ret < 0 ? ret : 0;
|
|
}
|
|
|
|
int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
|
|
{
|
|
struct qcom_scm_desc desc = {0};
|
|
struct arm_smccc_res res;
|
|
|
|
desc.args[0] = addr;
|
|
desc.args[1] = val;
|
|
desc.arginfo = QCOM_SCM_ARGS(2);
|
|
|
|
return qcom_scm_call(dev, QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE,
|
|
&desc, &res);
|
|
}
|