f3573b8f90
Small Things:
- Move OpenRISC docs into Documentation and clean them up
- Document previously undocumented devicetree bindings
- Update the or1ksim dts to use stdout-path
OpenRISC SMP support details:
- First the "use shadow registers" and "define CPU_BIG_ENDIAN as true"
get the architecture ready for SMP.
- The "add 1 and 2 byte cmpxchg support" and "use qspinlocks and
qrwlocks" add the SMP locking infrastructure as needed. Using the
qspinlocks and qrwlocks as suggested by Peter Z while reviewing the
original spinlocks implementation.
- The "support for ompic" adds a new irqchip device which is used for
IPI communication to support SMP.
- The "initial SMP support" adds smp.c and makes changes to all of the
necessary data-structures to be per-cpu.
- The remaining patches are bug fixes and debug helpers which I wanted
to keep separate from the "initial SMP support" in order to allow them
to be reviewed on their own. This includes:
- add cacheflush support to fix icache aliasing
- fix initial preempt state for secondary cpu tasks
- sleep instead of spin on secondary wait
- support framepointers and STACKTRACE_SUPPORT
- enable LOCKDEP_SUPPORT and irqflags tracing
- timer sync: Add tick timer sync logic
- fix possible deadlock in timer sync, pointed out by mips guys
Note: the irqchip patch was reviewed with Marc and we agreed to push it
together with these patches.
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Merge tag 'for-linus' of git://github.com/openrisc/linux
Pull OpenRISC updates from Stafford Horne:
"The OpenRISC work is a bit more interesting this time, adding SMP
support and a few general cleanups.
Small Things:
- Move OpenRISC docs into Documentation and clean them up
- Document previously undocumented devicetree bindings
- Update the or1ksim dts to use stdout-path
OpenRISC SMP support details:
- First the "use shadow registers" and "define CPU_BIG_ENDIAN as
true" get the architecture ready for SMP.
- The "add 1 and 2 byte cmpxchg support" and "use qspinlocks and
qrwlocks" add the SMP locking infrastructure as needed. Using the
qspinlocks and qrwlocks as suggested by Peter Z while reviewing the
original spinlocks implementation.
- The "support for ompic" adds a new irqchip device which is used for
IPI communication to support SMP.
- The "initial SMP support" adds smp.c and makes changes to all of
the necessary data-structures to be per-cpu.
The remaining patches are bug fixes and debug helpers which I wanted
to keep separate from the "initial SMP support" in order to allow them
to be reviewed on their own. This includes:
- add cacheflush support to fix icache aliasing
- fix initial preempt state for secondary cpu tasks
- sleep instead of spin on secondary wait
- support framepointers and STACKTRACE_SUPPORT
- enable LOCKDEP_SUPPORT and irqflags tracing
- timer sync: Add tick timer sync logic
- fix possible deadlock in timer sync, pointed out by mips guys
Note: the irqchip patch was reviewed with Marc and we agreed to push
it together with these patches"
* tag 'for-linus' of git://github.com/openrisc/linux:
openrisc: fix possible deadlock scenario during timer sync
openrisc: pass endianness info to sparse
openrisc: add tick timer multi-core sync logic
openrisc: enable LOCKDEP_SUPPORT and irqflags tracing
openrisc: support framepointers and STACKTRACE_SUPPORT
openrisc: add simple_smp dts and defconfig for simulators
openrisc: add cacheflush support to fix icache aliasing
openrisc: sleep instead of spin on secondary wait
openrisc: fix initial preempt state for secondary cpu tasks
openrisc: initial SMP support
irqchip: add initial support for ompic
dt-bindings: add openrisc to vendor prefixes list
openrisc: use qspinlocks and qrwlocks
openrisc: add 1 and 2 byte cmpxchg support
openrisc: use shadow registers to save regs on exception
dt-bindings: openrisc: Add OpenRISC platform SoC
Documentation: openrisc: Updates to README
Documentation: Move OpenRISC docs out of arch/
MAINTAINERS: Add OpenRISC pic maintainer
openrisc: dts: or1ksim: Add stdout-path
84 lines
3.8 KiB
Makefile
84 lines
3.8 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_IRQCHIP) += irqchip.o
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obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
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obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
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obj-$(CONFIG_ATH79) += irq-ath79-misc.o
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
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obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
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obj-$(CONFIG_FARADAY_FTINTC010) += irq-ftintc010.o
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obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o
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obj-$(CONFIG_ARCH_LPC32XX) += irq-lpc32xx.o
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obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
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obj-$(CONFIG_IRQ_MXS) += irq-mxs.o
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obj-$(CONFIG_ARCH_TEGRA) += irq-tegra.o
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obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
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obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
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obj-$(CONFIG_METAG) += irq-metag-ext.o
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obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
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obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o
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obj-$(CONFIG_OMPIC) += irq-ompic.o
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obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o
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obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
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obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o
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obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
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obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o
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obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
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obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o
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obj-$(CONFIG_ARM_GIC_PM) += irq-gic-pm.o
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obj-$(CONFIG_ARCH_REALVIEW) += irq-gic-realview.o
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obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o
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obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o
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obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-pci-msi.o irq-gic-v3-its-platform-msi.o irq-gic-v4.o
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obj-$(CONFIG_PARTITION_PERCPU) += irq-partition-percpu.o
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obj-$(CONFIG_HISILICON_IRQ_MBIGEN) += irq-mbigen.o
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obj-$(CONFIG_ARM_NVIC) += irq-nvic.o
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obj-$(CONFIG_ARM_VIC) += irq-vic.o
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obj-$(CONFIG_ARMADA_370_XP_IRQ) += irq-armada-370-xp.o
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obj-$(CONFIG_ATMEL_AIC_IRQ) += irq-atmel-aic-common.o irq-atmel-aic.o
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obj-$(CONFIG_ATMEL_AIC5_IRQ) += irq-atmel-aic-common.o irq-atmel-aic5.o
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obj-$(CONFIG_I8259) += irq-i8259.o
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obj-$(CONFIG_IMGPDC_IRQ) += irq-imgpdc.o
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obj-$(CONFIG_IRQ_MIPS_CPU) += irq-mips-cpu.o
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obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o
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obj-$(CONFIG_JCORE_AIC) += irq-jcore-aic.o
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obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
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obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
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obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
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obj-$(CONFIG_ARCH_NSPIRE) += irq-zevio.o
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obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o
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obj-$(CONFIG_ST_IRQCHIP) += irq-st.o
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obj-$(CONFIG_TANGO_IRQ) += irq-tango.o
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obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o
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obj-$(CONFIG_TS4800_IRQ) += irq-ts4800.o
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obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o
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obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o
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obj-$(CONFIG_XILINX_INTC) += irq-xilinx-intc.o
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obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
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obj-$(CONFIG_SOC_VF610) += irq-vf610-mscm-ir.o
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obj-$(CONFIG_BCM6345_L1_IRQ) += irq-bcm6345-l1.o
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obj-$(CONFIG_BCM7038_L1_IRQ) += irq-bcm7038-l1.o
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obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o
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obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o
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obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o
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obj-$(CONFIG_MIPS_GIC) += irq-mips-gic.o
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obj-$(CONFIG_ARCH_MEDIATEK) += irq-mtk-sysirq.o irq-mtk-cirq.o
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obj-$(CONFIG_ARCH_DIGICOLOR) += irq-digicolor.o
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obj-$(CONFIG_RENESAS_H8300H_INTC) += irq-renesas-h8300h.o
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obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o
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obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o
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obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
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obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
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obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o
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obj-$(CONFIG_MVEBU_GICP) += irq-mvebu-gicp.o
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obj-$(CONFIG_MVEBU_ICU) += irq-mvebu-icu.o
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obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
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obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o
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obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
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obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
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obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o
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obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
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obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
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obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o
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