f2c73464d7
This is the branch where we usually queue up cleanup efforts, moving
drivers out of the architecture directory, header file restructuring,
etc. Sometimes they tangle with new development so it's hard to keep it
strictly to cleanups.
Some of the things included in this branch are:
* Atmel SAMA5 conversion to common clock
* Reset framework conversion for tegra platforms
- Some of this depends on tegra clock driver reworks that are shared with Mike
Turquette's clk tree.
* Tegra DMA refactoring, which are shared branches with the DMA tree.
* Removal of some header files on exynos to prepare for multiplatform
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Merge tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Olof Johansson:
"This is the branch where we usually queue up cleanup efforts, moving
drivers out of the architecture directory, header file restructuring,
etc. Sometimes they tangle with new development so it's hard to keep
it strictly to cleanups.
Some of the things included in this branch are:
* Atmel SAMA5 conversion to common clock
* Reset framework conversion for tegra platforms
- Some of this depends on tegra clock driver reworks that are shared
with Mike Turquette's clk tree.
* Tegra DMA refactoring, which are shared branches with the DMA tree.
* Removal of some header files on exynos to prepare for
multiplatform"
* tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (169 commits)
ARM: mvebu: move Armada 370/XP specific definitions to armada-370-xp.h
ARM: mvebu: remove prototypes of non-existing functions from common.h
ARM: mvebu: move ARMADA_XP_MAX_CPUS to armada-370-xp.h
serial: sh-sci: Rework baud rate calculation
serial: sh-sci: Compute overrun_bit without using baud rate algo
serial: sh-sci: Remove unused GPIO request code
serial: sh-sci: Move overrun_bit and error_mask fields out of pdata
serial: sh-sci: Support resources passed through platform resources
serial: sh-sci: Don't check IRQ in verify port operation
serial: sh-sci: Set the UPF_FIXED_PORT flag
serial: sh-sci: Remove duplicate interrupt check in verify port op
serial: sh-sci: Simplify baud rate calculation algorithms
serial: sh-sci: Remove baud rate calculation algorithm 5
serial: sh-sci: Sort headers alphabetically
ARM: EXYNOS: Kill exynos_pm_late_initcall()
ARM: EXYNOS: Consolidate selection of PM_GENERIC_DOMAINS for Exynos4
ARM: at91: switch Calao QIL-A9260 board to DT
clk: at91: fix pmc_clk_ids data type attriubte
PM / devfreq: use inclusion <mach/map.h> instead of <plat/map-s5p.h>
ARM: EXYNOS: remove <mach/regs-clock.h> for exynos
...
532 lines
13 KiB
C
532 lines
13 KiB
C
/*
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* Copyright (C) 2007 Atmel Corporation.
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* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* Under GPLv2
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*/
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <linux/pm.h>
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#include <linux/of_address.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/clk/at91_pmc.h>
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#include <asm/system_misc.h>
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#include <asm/mach/map.h>
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#include <mach/hardware.h>
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#include <mach/cpu.h>
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#include <mach/at91_dbgu.h>
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#include "at91_shdwc.h"
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#include "soc.h"
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#include "generic.h"
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#include "pm.h"
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struct at91_init_soc __initdata at91_boot_soc;
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struct at91_socinfo at91_soc_initdata;
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EXPORT_SYMBOL(at91_soc_initdata);
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void __init at91rm9200_set_type(int type)
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{
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if (type == ARCH_REVISON_9200_PQFP)
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at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
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else
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at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
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pr_info("AT91: filled in soc subtype: %s\n",
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at91_get_soc_subtype(&at91_soc_initdata));
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}
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void __init at91_init_irq_default(void)
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{
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at91_init_interrupts(at91_boot_soc.default_irq_priority);
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}
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void __init at91_init_interrupts(unsigned int *priority)
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{
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/* Initialize the AIC interrupt controller */
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at91_aic_init(priority, at91_boot_soc.extern_irq);
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/* Enable GPIO interrupts */
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at91_gpio_irq_setup();
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}
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void __iomem *at91_ramc_base[2];
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EXPORT_SYMBOL_GPL(at91_ramc_base);
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void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
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{
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if (id < 0 || id > 1) {
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pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
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BUG();
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}
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at91_ramc_base[id] = ioremap(addr, size);
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if (!at91_ramc_base[id])
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panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
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}
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static struct map_desc sram_desc[2] __initdata;
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void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
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{
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struct map_desc *desc = &sram_desc[bank];
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desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
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if (bank > 0)
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desc->virtual -= sram_desc[bank - 1].length;
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desc->pfn = __phys_to_pfn(base);
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desc->length = length;
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desc->type = MT_MEMORY_RWX_NONCACHED;
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pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
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base, length, desc->virtual);
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iotable_init(desc, 1);
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}
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static struct map_desc at91_io_desc __initdata __maybe_unused = {
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.virtual = (unsigned long)AT91_VA_BASE_SYS,
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.pfn = __phys_to_pfn(AT91_BASE_SYS),
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.length = SZ_16K,
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.type = MT_DEVICE,
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};
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static void __init soc_detect(u32 dbgu_base)
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{
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u32 cidr, socid;
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cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
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socid = cidr & ~AT91_CIDR_VERSION;
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switch (socid) {
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case ARCH_ID_AT91RM9200:
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at91_soc_initdata.type = AT91_SOC_RM9200;
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if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
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at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
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at91_boot_soc = at91rm9200_soc;
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break;
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case ARCH_ID_AT91SAM9260:
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at91_soc_initdata.type = AT91_SOC_SAM9260;
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at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
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at91_boot_soc = at91sam9260_soc;
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break;
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case ARCH_ID_AT91SAM9261:
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at91_soc_initdata.type = AT91_SOC_SAM9261;
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at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
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at91_boot_soc = at91sam9261_soc;
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break;
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case ARCH_ID_AT91SAM9263:
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at91_soc_initdata.type = AT91_SOC_SAM9263;
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at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
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at91_boot_soc = at91sam9263_soc;
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break;
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case ARCH_ID_AT91SAM9G20:
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at91_soc_initdata.type = AT91_SOC_SAM9G20;
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at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
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at91_boot_soc = at91sam9260_soc;
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break;
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case ARCH_ID_AT91SAM9G45:
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at91_soc_initdata.type = AT91_SOC_SAM9G45;
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if (cidr == ARCH_ID_AT91SAM9G45ES)
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at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
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at91_boot_soc = at91sam9g45_soc;
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break;
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case ARCH_ID_AT91SAM9RL64:
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at91_soc_initdata.type = AT91_SOC_SAM9RL;
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at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
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at91_boot_soc = at91sam9rl_soc;
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break;
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case ARCH_ID_AT91SAM9X5:
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at91_soc_initdata.type = AT91_SOC_SAM9X5;
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at91_boot_soc = at91sam9x5_soc;
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break;
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case ARCH_ID_AT91SAM9N12:
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at91_soc_initdata.type = AT91_SOC_SAM9N12;
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at91_boot_soc = at91sam9n12_soc;
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break;
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case ARCH_ID_SAMA5D3:
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at91_soc_initdata.type = AT91_SOC_SAMA5D3;
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at91_boot_soc = sama5d3_soc;
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break;
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}
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/* at91sam9g10 */
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if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
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at91_soc_initdata.type = AT91_SOC_SAM9G10;
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at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
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at91_boot_soc = at91sam9261_soc;
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}
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/* at91sam9xe */
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else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
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at91_soc_initdata.type = AT91_SOC_SAM9260;
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at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
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at91_boot_soc = at91sam9260_soc;
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}
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if (!at91_soc_is_detected())
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return;
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at91_soc_initdata.cidr = cidr;
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/* sub version of soc */
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at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
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if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
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switch (at91_soc_initdata.exid) {
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case ARCH_EXID_AT91SAM9M10:
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at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
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break;
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case ARCH_EXID_AT91SAM9G46:
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at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
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break;
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case ARCH_EXID_AT91SAM9M11:
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at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
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break;
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}
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}
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if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
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switch (at91_soc_initdata.exid) {
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case ARCH_EXID_AT91SAM9G15:
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at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
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break;
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case ARCH_EXID_AT91SAM9G35:
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at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
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break;
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case ARCH_EXID_AT91SAM9X35:
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at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
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break;
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case ARCH_EXID_AT91SAM9G25:
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at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
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break;
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case ARCH_EXID_AT91SAM9X25:
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at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
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break;
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}
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}
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if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
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switch (at91_soc_initdata.exid) {
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case ARCH_EXID_SAMA5D31:
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at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
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break;
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case ARCH_EXID_SAMA5D33:
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at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
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break;
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case ARCH_EXID_SAMA5D34:
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at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
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break;
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case ARCH_EXID_SAMA5D35:
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at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
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break;
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}
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}
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}
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static const char *soc_name[] = {
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[AT91_SOC_RM9200] = "at91rm9200",
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[AT91_SOC_SAM9260] = "at91sam9260",
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[AT91_SOC_SAM9261] = "at91sam9261",
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[AT91_SOC_SAM9263] = "at91sam9263",
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[AT91_SOC_SAM9G10] = "at91sam9g10",
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[AT91_SOC_SAM9G20] = "at91sam9g20",
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[AT91_SOC_SAM9G45] = "at91sam9g45",
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[AT91_SOC_SAM9RL] = "at91sam9rl",
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[AT91_SOC_SAM9X5] = "at91sam9x5",
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[AT91_SOC_SAM9N12] = "at91sam9n12",
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[AT91_SOC_SAMA5D3] = "sama5d3",
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[AT91_SOC_UNKNOWN] = "Unknown",
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};
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const char *at91_get_soc_type(struct at91_socinfo *c)
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{
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return soc_name[c->type];
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}
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EXPORT_SYMBOL(at91_get_soc_type);
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static const char *soc_subtype_name[] = {
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[AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
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[AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
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[AT91_SOC_SAM9XE] = "at91sam9xe",
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[AT91_SOC_SAM9G45ES] = "at91sam9g45es",
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[AT91_SOC_SAM9M10] = "at91sam9m10",
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[AT91_SOC_SAM9G46] = "at91sam9g46",
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[AT91_SOC_SAM9M11] = "at91sam9m11",
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[AT91_SOC_SAM9G15] = "at91sam9g15",
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[AT91_SOC_SAM9G35] = "at91sam9g35",
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[AT91_SOC_SAM9X35] = "at91sam9x35",
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[AT91_SOC_SAM9G25] = "at91sam9g25",
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[AT91_SOC_SAM9X25] = "at91sam9x25",
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[AT91_SOC_SAMA5D31] = "sama5d31",
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[AT91_SOC_SAMA5D33] = "sama5d33",
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[AT91_SOC_SAMA5D34] = "sama5d34",
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[AT91_SOC_SAMA5D35] = "sama5d35",
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[AT91_SOC_SUBTYPE_NONE] = "None",
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[AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
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};
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const char *at91_get_soc_subtype(struct at91_socinfo *c)
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{
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return soc_subtype_name[c->subtype];
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}
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EXPORT_SYMBOL(at91_get_soc_subtype);
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void __init at91_map_io(void)
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{
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/* Map peripherals */
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iotable_init(&at91_io_desc, 1);
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at91_soc_initdata.type = AT91_SOC_UNKNOWN;
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at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
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soc_detect(AT91_BASE_DBGU0);
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if (!at91_soc_is_detected())
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soc_detect(AT91_BASE_DBGU1);
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if (!at91_soc_is_detected())
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panic("AT91: Impossible to detect the SOC type");
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pr_info("AT91: Detected soc type: %s\n",
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at91_get_soc_type(&at91_soc_initdata));
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if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
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pr_info("AT91: Detected soc subtype: %s\n",
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at91_get_soc_subtype(&at91_soc_initdata));
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if (!at91_soc_is_enabled())
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panic("AT91: Soc not enabled");
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if (at91_boot_soc.map_io)
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at91_boot_soc.map_io();
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}
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void __iomem *at91_shdwc_base = NULL;
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static void at91sam9_poweroff(void)
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{
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at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
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}
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void __init at91_ioremap_shdwc(u32 base_addr)
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{
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at91_shdwc_base = ioremap(base_addr, 16);
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if (!at91_shdwc_base)
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panic("Impossible to ioremap at91_shdwc_base\n");
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pm_power_off = at91sam9_poweroff;
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}
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void __iomem *at91_rstc_base;
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void __init at91_ioremap_rstc(u32 base_addr)
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{
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at91_rstc_base = ioremap(base_addr, 16);
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if (!at91_rstc_base)
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panic("Impossible to ioremap at91_rstc_base\n");
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}
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void __iomem *at91_matrix_base;
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EXPORT_SYMBOL_GPL(at91_matrix_base);
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void __init at91_ioremap_matrix(u32 base_addr)
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{
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at91_matrix_base = ioremap(base_addr, 512);
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if (!at91_matrix_base)
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panic("Impossible to ioremap at91_matrix_base\n");
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}
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#if defined(CONFIG_OF)
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static struct of_device_id rstc_ids[] = {
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{ .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
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{ .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
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{ /*sentinel*/ }
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};
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static void at91_dt_rstc(void)
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{
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struct device_node *np;
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const struct of_device_id *of_id;
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np = of_find_matching_node(NULL, rstc_ids);
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if (!np)
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panic("unable to find compatible rstc node in dtb\n");
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at91_rstc_base = of_iomap(np, 0);
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if (!at91_rstc_base)
|
|
panic("unable to map rstc cpu registers\n");
|
|
|
|
of_id = of_match_node(rstc_ids, np);
|
|
if (!of_id)
|
|
panic("AT91: rtsc no restart function available\n");
|
|
|
|
arm_pm_restart = of_id->data;
|
|
|
|
of_node_put(np);
|
|
}
|
|
|
|
static struct of_device_id ramc_ids[] = {
|
|
{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
|
|
{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
|
|
{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
|
|
{ /*sentinel*/ }
|
|
};
|
|
|
|
static void at91_dt_ramc(void)
|
|
{
|
|
struct device_node *np;
|
|
const struct of_device_id *of_id;
|
|
|
|
np = of_find_matching_node(NULL, ramc_ids);
|
|
if (!np)
|
|
panic("unable to find compatible ram controller node in dtb\n");
|
|
|
|
at91_ramc_base[0] = of_iomap(np, 0);
|
|
if (!at91_ramc_base[0])
|
|
panic("unable to map ramc[0] cpu registers\n");
|
|
/* the controller may have 2 banks */
|
|
at91_ramc_base[1] = of_iomap(np, 1);
|
|
|
|
of_id = of_match_node(ramc_ids, np);
|
|
if (!of_id)
|
|
pr_warn("AT91: ramc no standby function available\n");
|
|
else
|
|
at91_pm_set_standby(of_id->data);
|
|
|
|
of_node_put(np);
|
|
}
|
|
|
|
static struct of_device_id shdwc_ids[] = {
|
|
{ .compatible = "atmel,at91sam9260-shdwc", },
|
|
{ .compatible = "atmel,at91sam9rl-shdwc", },
|
|
{ .compatible = "atmel,at91sam9x5-shdwc", },
|
|
{ /*sentinel*/ }
|
|
};
|
|
|
|
static const char *shdwc_wakeup_modes[] = {
|
|
[AT91_SHDW_WKMODE0_NONE] = "none",
|
|
[AT91_SHDW_WKMODE0_HIGH] = "high",
|
|
[AT91_SHDW_WKMODE0_LOW] = "low",
|
|
[AT91_SHDW_WKMODE0_ANYLEVEL] = "any",
|
|
};
|
|
|
|
const int at91_dtget_shdwc_wakeup_mode(struct device_node *np)
|
|
{
|
|
const char *pm;
|
|
int err, i;
|
|
|
|
err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
|
|
if (err < 0)
|
|
return AT91_SHDW_WKMODE0_ANYLEVEL;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
|
|
if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
|
|
return i;
|
|
|
|
return -ENODEV;
|
|
}
|
|
|
|
static void at91_dt_shdwc(void)
|
|
{
|
|
struct device_node *np;
|
|
int wakeup_mode;
|
|
u32 reg;
|
|
u32 mode = 0;
|
|
|
|
np = of_find_matching_node(NULL, shdwc_ids);
|
|
if (!np) {
|
|
pr_debug("AT91: unable to find compatible shutdown (shdwc) controller node in dtb\n");
|
|
return;
|
|
}
|
|
|
|
at91_shdwc_base = of_iomap(np, 0);
|
|
if (!at91_shdwc_base)
|
|
panic("AT91: unable to map shdwc cpu registers\n");
|
|
|
|
wakeup_mode = at91_dtget_shdwc_wakeup_mode(np);
|
|
if (wakeup_mode < 0) {
|
|
pr_warn("AT91: shdwc unknown wakeup mode\n");
|
|
goto end;
|
|
}
|
|
|
|
if (!of_property_read_u32(np, "atmel,wakeup-counter", ®)) {
|
|
if (reg > AT91_SHDW_CPTWK0_MAX) {
|
|
pr_warn("AT91: shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n",
|
|
reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
|
|
reg = AT91_SHDW_CPTWK0_MAX;
|
|
}
|
|
mode |= AT91_SHDW_CPTWK0_(reg);
|
|
}
|
|
|
|
if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
|
|
mode |= AT91_SHDW_RTCWKEN;
|
|
|
|
if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
|
|
mode |= AT91_SHDW_RTTWKEN;
|
|
|
|
at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
|
|
|
|
end:
|
|
pm_power_off = at91sam9_poweroff;
|
|
|
|
of_node_put(np);
|
|
}
|
|
|
|
void __init at91rm9200_dt_initialize(void)
|
|
{
|
|
at91_dt_ramc();
|
|
|
|
/* Init clock subsystem */
|
|
at91_dt_clock_init();
|
|
|
|
/* Register the processor-specific clocks */
|
|
if (at91_boot_soc.register_clocks)
|
|
at91_boot_soc.register_clocks();
|
|
|
|
at91_boot_soc.init();
|
|
}
|
|
|
|
void __init at91_dt_initialize(void)
|
|
{
|
|
at91_dt_rstc();
|
|
at91_dt_ramc();
|
|
at91_dt_shdwc();
|
|
|
|
/* Init clock subsystem */
|
|
at91_dt_clock_init();
|
|
|
|
/* Register the processor-specific clocks */
|
|
if (at91_boot_soc.register_clocks)
|
|
at91_boot_soc.register_clocks();
|
|
|
|
if (at91_boot_soc.init)
|
|
at91_boot_soc.init();
|
|
}
|
|
#endif
|
|
|
|
void __init at91_initialize(unsigned long main_clock)
|
|
{
|
|
at91_boot_soc.ioremap_registers();
|
|
|
|
/* Init clock subsystem */
|
|
at91_clock_init(main_clock);
|
|
|
|
/* Register the processor-specific clocks */
|
|
at91_boot_soc.register_clocks();
|
|
|
|
at91_boot_soc.init();
|
|
|
|
pinctrl_provide_dummies();
|
|
}
|