f2a89d3b2b
The ARM architected timer specification mandates that the interrupt associated with each timer is level triggered (which corresponds to the "counter >= comparator" condition). A number of DTs are being remarkably creative, declaring the interrupt to be edge triggered. A quick look at the TRM for the corresponding ARM CPUs clearly shows that this is wrong, and I've corrected those. For non-ARM designs (and in the absence of a publicly available TRM), I've made them active low as well, which can't be completely wrong as the GIC cannot disinguish between level low and level high. The respective maintainers are of course welcome to prove me wrong. While I was at it, I took the liberty to fix a couple of related issue, such as some spurious affinity bits on ThunderX, and their complete absence on ls1043a (both of which seem to be related to copy-pasting from other DTs). Acked-by: Duc Dang <dhdang@apm.com> Acked-by: Carlo Caione <carlo@endlessm.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
719 lines
19 KiB
Plaintext
719 lines
19 KiB
Plaintext
/*
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* Device Tree Include file for Freescale Layerscape-2080A family SoC.
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*
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* Copyright (C) 2014-2015, Freescale Semiconductor
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*
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* Bhupesh Sharma <bhupesh.sharma@freescale.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPLv2 or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/ {
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compatible = "fsl,ls2080a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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/*
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* We expect the enable-method for cpu's to be "psci", but this
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* is dependent on the SoC FW, which will fill this in.
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*
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* Currently supported enable-method is psci v0.2
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*/
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/* We have 4 clusters having 2 Cortex-A57 cores each */
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&cluster0_l2>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&cluster0_l2>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x100>;
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clocks = <&clockgen 1 1>;
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next-level-cache = <&cluster1_l2>;
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};
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cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x101>;
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clocks = <&clockgen 1 1>;
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next-level-cache = <&cluster1_l2>;
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};
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cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x200>;
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clocks = <&clockgen 1 2>;
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next-level-cache = <&cluster2_l2>;
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};
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cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x201>;
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clocks = <&clockgen 1 2>;
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next-level-cache = <&cluster2_l2>;
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};
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cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x300>;
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clocks = <&clockgen 1 3>;
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next-level-cache = <&cluster3_l2>;
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};
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cpu@301 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x301>;
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clocks = <&clockgen 1 3>;
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next-level-cache = <&cluster3_l2>;
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};
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cluster0_l2: l2-cache0 {
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compatible = "cache";
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};
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cluster1_l2: l2-cache1 {
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compatible = "cache";
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};
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cluster2_l2: l2-cache2 {
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compatible = "cache";
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};
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cluster3_l2: l2-cache3 {
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compatible = "cache";
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0 0x80000000>;
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/* DRAM space - 1, size : 2 GB DRAM */
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};
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sysclk: sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "sysclk";
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};
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gic: interrupt-controller@6000000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
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<0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
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<0x0 0x0c0c0000 0 0x2000>, /* GICC */
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<0x0 0x0c0d0000 0 0x1000>, /* GICH */
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<0x0 0x0c0e0000 0 0x20000>; /* GICV */
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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interrupts = <1 9 0x4>;
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its: gic-its@6020000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0x6020000 0 0x20000>;
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};
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};
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rstcr: syscon@1e60000 {
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compatible = "fsl,ls2080a-rstcr", "syscon";
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reg = <0x0 0x1e60000 0x0 0x4>;
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};
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reboot {
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compatible ="syscon-reboot";
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regmap = <&rstcr>;
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offset = <0x0>;
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mask = <0x2>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
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<1 14 4>, /* Physical Non-Secure PPI, active-low */
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<1 11 4>, /* Virtual PPI, active-low */
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<1 10 4>; /* Hypervisor PPI, active-low */
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clockgen: clocking@1300000 {
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compatible = "fsl,ls2080a-clockgen";
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reg = <0 0x1300000 0 0xa0000>;
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#clock-cells = <2>;
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clocks = <&sysclk>;
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};
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serial0: serial@21c0500 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0500 0x0 0x100>;
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clocks = <&clockgen 4 3>;
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interrupts = <0 32 0x4>; /* Level high type */
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};
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serial1: serial@21c0600 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0600 0x0 0x100>;
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clocks = <&clockgen 4 3>;
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interrupts = <0 32 0x4>; /* Level high type */
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};
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cluster1_core0_watchdog: wdt@c000000 {
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compatible = "arm,sp805-wdt", "arm,primecell";
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reg = <0x0 0xc000000 0x0 0x1000>;
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clocks = <&clockgen 4 3>, <&clockgen 4 3>;
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clock-names = "apb_pclk", "wdog_clk";
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};
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cluster1_core1_watchdog: wdt@c010000 {
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compatible = "arm,sp805-wdt", "arm,primecell";
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reg = <0x0 0xc010000 0x0 0x1000>;
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clocks = <&clockgen 4 3>, <&clockgen 4 3>;
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clock-names = "apb_pclk", "wdog_clk";
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};
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cluster2_core0_watchdog: wdt@c100000 {
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compatible = "arm,sp805-wdt", "arm,primecell";
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reg = <0x0 0xc100000 0x0 0x1000>;
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clocks = <&clockgen 4 3>, <&clockgen 4 3>;
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clock-names = "apb_pclk", "wdog_clk";
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};
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cluster2_core1_watchdog: wdt@c110000 {
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compatible = "arm,sp805-wdt", "arm,primecell";
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reg = <0x0 0xc110000 0x0 0x1000>;
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clocks = <&clockgen 4 3>, <&clockgen 4 3>;
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clock-names = "apb_pclk", "wdog_clk";
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};
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cluster3_core0_watchdog: wdt@c200000 {
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compatible = "arm,sp805-wdt", "arm,primecell";
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reg = <0x0 0xc200000 0x0 0x1000>;
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clocks = <&clockgen 4 3>, <&clockgen 4 3>;
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clock-names = "apb_pclk", "wdog_clk";
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};
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cluster3_core1_watchdog: wdt@c210000 {
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compatible = "arm,sp805-wdt", "arm,primecell";
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reg = <0x0 0xc210000 0x0 0x1000>;
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clocks = <&clockgen 4 3>, <&clockgen 4 3>;
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clock-names = "apb_pclk", "wdog_clk";
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};
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cluster4_core0_watchdog: wdt@c300000 {
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compatible = "arm,sp805-wdt", "arm,primecell";
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reg = <0x0 0xc300000 0x0 0x1000>;
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clocks = <&clockgen 4 3>, <&clockgen 4 3>;
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clock-names = "apb_pclk", "wdog_clk";
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};
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cluster4_core1_watchdog: wdt@c310000 {
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compatible = "arm,sp805-wdt", "arm,primecell";
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reg = <0x0 0xc310000 0x0 0x1000>;
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clocks = <&clockgen 4 3>, <&clockgen 4 3>;
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clock-names = "apb_pclk", "wdog_clk";
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};
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fsl_mc: fsl-mc@80c000000 {
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compatible = "fsl,qoriq-mc";
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reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
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<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
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msi-parent = <&its>;
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#address-cells = <3>;
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#size-cells = <1>;
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/*
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* Region type 0x0 - MC portals
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* Region type 0x1 - QBMAN portals
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*/
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ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
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0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
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/*
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* Define the maximum number of MACs present on the SoC.
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*/
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dpmacs {
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#address-cells = <1>;
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#size-cells = <0>;
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dpmac1: dpmac@1 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x1>;
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};
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dpmac2: dpmac@2 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x2>;
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};
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dpmac3: dpmac@3 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x3>;
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};
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dpmac4: dpmac@4 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x4>;
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};
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dpmac5: dpmac@5 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x5>;
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};
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dpmac6: dpmac@6 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x6>;
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};
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dpmac7: dpmac@7 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x7>;
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};
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dpmac8: dpmac@8 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x8>;
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};
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dpmac9: dpmac@9 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x9>;
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};
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dpmac10: dpmac@a {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0xa>;
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};
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dpmac11: dpmac@b {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0xb>;
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};
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dpmac12: dpmac@c {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0xc>;
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};
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dpmac13: dpmac@d {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0xd>;
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};
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dpmac14: dpmac@e {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0xe>;
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};
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dpmac15: dpmac@f {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0xf>;
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};
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dpmac16: dpmac@10 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x10>;
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};
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};
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};
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smmu: iommu@5000000 {
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compatible = "arm,mmu-500";
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reg = <0 0x5000000 0 0x800000>;
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#global-interrupts = <12>;
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interrupts = <0 13 4>, /* global secure fault */
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<0 14 4>, /* combined secure interrupt */
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<0 15 4>, /* global non-secure fault */
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<0 16 4>, /* combined non-secure interrupt */
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/* performance counter interrupts 0-7 */
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<0 211 4>, <0 212 4>,
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<0 213 4>, <0 214 4>,
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<0 215 4>, <0 216 4>,
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<0 217 4>, <0 218 4>,
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/* per context interrupt, 64 interrupts */
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<0 146 4>, <0 147 4>,
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<0 148 4>, <0 149 4>,
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<0 150 4>, <0 151 4>,
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<0 152 4>, <0 153 4>,
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<0 154 4>, <0 155 4>,
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<0 156 4>, <0 157 4>,
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<0 158 4>, <0 159 4>,
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<0 160 4>, <0 161 4>,
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<0 162 4>, <0 163 4>,
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<0 164 4>, <0 165 4>,
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<0 166 4>, <0 167 4>,
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<0 168 4>, <0 169 4>,
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<0 170 4>, <0 171 4>,
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<0 172 4>, <0 173 4>,
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<0 174 4>, <0 175 4>,
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<0 176 4>, <0 177 4>,
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<0 178 4>, <0 179 4>,
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<0 180 4>, <0 181 4>,
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<0 182 4>, <0 183 4>,
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<0 184 4>, <0 185 4>,
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<0 186 4>, <0 187 4>,
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<0 188 4>, <0 189 4>,
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<0 190 4>, <0 191 4>,
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<0 192 4>, <0 193 4>,
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<0 194 4>, <0 195 4>,
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<0 196 4>, <0 197 4>,
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<0 198 4>, <0 199 4>,
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<0 200 4>, <0 201 4>,
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<0 202 4>, <0 203 4>,
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<0 204 4>, <0 205 4>,
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<0 206 4>, <0 207 4>,
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<0 208 4>, <0 209 4>;
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mmu-masters = <&fsl_mc 0x300 0>;
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};
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dspi: dspi@2100000 {
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status = "disabled";
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compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2100000 0x0 0x10000>;
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interrupts = <0 26 0x4>; /* Level high type */
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clocks = <&clockgen 4 3>;
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clock-names = "dspi";
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spi-num-chipselects = <5>;
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bus-num = <0>;
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};
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esdhc: esdhc@2140000 {
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status = "disabled";
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compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
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reg = <0x0 0x2140000 0x0 0x10000>;
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interrupts = <0 28 0x4>; /* Level high type */
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clock-frequency = <0>; /* Updated by bootloader */
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voltage-ranges = <1800 1800 3300 3300>;
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sdhci,auto-cmd12;
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little-endian;
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bus-width = <4>;
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};
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gpio0: gpio@2300000 {
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compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
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reg = <0x0 0x2300000 0x0 0x10000>;
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interrupts = <0 36 0x4>; /* Level high type */
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gpio-controller;
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little-endian;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@2310000 {
|
|
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
|
|
reg = <0x0 0x2310000 0x0 0x10000>;
|
|
interrupts = <0 36 0x4>; /* Level high type */
|
|
gpio-controller;
|
|
little-endian;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio@2320000 {
|
|
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
|
|
reg = <0x0 0x2320000 0x0 0x10000>;
|
|
interrupts = <0 37 0x4>; /* Level high type */
|
|
gpio-controller;
|
|
little-endian;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio@2330000 {
|
|
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
|
|
reg = <0x0 0x2330000 0x0 0x10000>;
|
|
interrupts = <0 37 0x4>; /* Level high type */
|
|
gpio-controller;
|
|
little-endian;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
i2c0: i2c@2000000 {
|
|
status = "disabled";
|
|
compatible = "fsl,vf610-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x2000000 0x0 0x10000>;
|
|
interrupts = <0 34 0x4>; /* Level high type */
|
|
clock-names = "i2c";
|
|
clocks = <&clockgen 4 3>;
|
|
};
|
|
|
|
i2c1: i2c@2010000 {
|
|
status = "disabled";
|
|
compatible = "fsl,vf610-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x2010000 0x0 0x10000>;
|
|
interrupts = <0 34 0x4>; /* Level high type */
|
|
clock-names = "i2c";
|
|
clocks = <&clockgen 4 3>;
|
|
};
|
|
|
|
i2c2: i2c@2020000 {
|
|
status = "disabled";
|
|
compatible = "fsl,vf610-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x2020000 0x0 0x10000>;
|
|
interrupts = <0 35 0x4>; /* Level high type */
|
|
clock-names = "i2c";
|
|
clocks = <&clockgen 4 3>;
|
|
};
|
|
|
|
i2c3: i2c@2030000 {
|
|
status = "disabled";
|
|
compatible = "fsl,vf610-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x2030000 0x0 0x10000>;
|
|
interrupts = <0 35 0x4>; /* Level high type */
|
|
clock-names = "i2c";
|
|
clocks = <&clockgen 4 3>;
|
|
};
|
|
|
|
ifc: ifc@2240000 {
|
|
compatible = "fsl,ifc", "simple-bus";
|
|
reg = <0x0 0x2240000 0x0 0x20000>;
|
|
interrupts = <0 21 0x4>; /* Level high type */
|
|
little-endian;
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
|
|
ranges = <0 0 0x5 0x80000000 0x08000000
|
|
2 0 0x5 0x30000000 0x00010000
|
|
3 0 0x5 0x20000000 0x00010000>;
|
|
};
|
|
|
|
qspi: quadspi@20c0000 {
|
|
status = "disabled";
|
|
compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x20c0000 0x0 0x10000>,
|
|
<0x0 0x20000000 0x0 0x10000000>;
|
|
reg-names = "QuadSPI", "QuadSPI-memory";
|
|
interrupts = <0 25 0x4>; /* Level high type */
|
|
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
|
clock-names = "qspi_en", "qspi";
|
|
};
|
|
|
|
pcie@3400000 {
|
|
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
|
|
"snps,dw-pcie";
|
|
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
|
0x10 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
reg-names = "regs", "config";
|
|
interrupts = <0 108 0x4>; /* Level high type */
|
|
interrupt-names = "intr";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
num-lanes = <4>;
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
msi-parent = <&its>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
|
|
<0000 0 0 2 &gic 0 0 0 110 4>,
|
|
<0000 0 0 3 &gic 0 0 0 111 4>,
|
|
<0000 0 0 4 &gic 0 0 0 112 4>;
|
|
};
|
|
|
|
pcie@3500000 {
|
|
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
|
|
"snps,dw-pcie";
|
|
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
|
|
0x12 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
reg-names = "regs", "config";
|
|
interrupts = <0 113 0x4>; /* Level high type */
|
|
interrupt-names = "intr";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
num-lanes = <4>;
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
msi-parent = <&its>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
|
|
<0000 0 0 2 &gic 0 0 0 115 4>,
|
|
<0000 0 0 3 &gic 0 0 0 116 4>,
|
|
<0000 0 0 4 &gic 0 0 0 117 4>;
|
|
};
|
|
|
|
pcie@3600000 {
|
|
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
|
|
"snps,dw-pcie";
|
|
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
|
|
0x14 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
reg-names = "regs", "config";
|
|
interrupts = <0 118 0x4>; /* Level high type */
|
|
interrupt-names = "intr";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
num-lanes = <8>;
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
msi-parent = <&its>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
|
|
<0000 0 0 2 &gic 0 0 0 120 4>,
|
|
<0000 0 0 3 &gic 0 0 0 121 4>,
|
|
<0000 0 0 4 &gic 0 0 0 122 4>;
|
|
};
|
|
|
|
pcie@3700000 {
|
|
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
|
|
"snps,dw-pcie";
|
|
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
|
|
0x16 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
reg-names = "regs", "config";
|
|
interrupts = <0 123 0x4>; /* Level high type */
|
|
interrupt-names = "intr";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
num-lanes = <4>;
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
msi-parent = <&its>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
|
|
<0000 0 0 2 &gic 0 0 0 125 4>,
|
|
<0000 0 0 3 &gic 0 0 0 126 4>,
|
|
<0000 0 0 4 &gic 0 0 0 127 4>;
|
|
};
|
|
|
|
sata0: sata@3200000 {
|
|
status = "disabled";
|
|
compatible = "fsl,ls2080a-ahci";
|
|
reg = <0x0 0x3200000 0x0 0x10000>;
|
|
interrupts = <0 133 0x4>; /* Level high type */
|
|
clocks = <&clockgen 4 3>;
|
|
};
|
|
|
|
sata1: sata@3210000 {
|
|
status = "disabled";
|
|
compatible = "fsl,ls2080a-ahci";
|
|
reg = <0x0 0x3210000 0x0 0x10000>;
|
|
interrupts = <0 136 0x4>; /* Level high type */
|
|
clocks = <&clockgen 4 3>;
|
|
};
|
|
|
|
usb0: usb3@3100000 {
|
|
status = "disabled";
|
|
compatible = "snps,dwc3";
|
|
reg = <0x0 0x3100000 0x0 0x10000>;
|
|
interrupts = <0 80 0x4>; /* Level high type */
|
|
dr_mode = "host";
|
|
snps,quirk-frame-length-adjustment = <0x20>;
|
|
snps,dis_rxdet_inp3_quirk;
|
|
};
|
|
|
|
usb1: usb3@3110000 {
|
|
status = "disabled";
|
|
compatible = "snps,dwc3";
|
|
reg = <0x0 0x3110000 0x0 0x10000>;
|
|
interrupts = <0 81 0x4>; /* Level high type */
|
|
dr_mode = "host";
|
|
snps,quirk-frame-length-adjustment = <0x20>;
|
|
snps,dis_rxdet_inp3_quirk;
|
|
};
|
|
|
|
ccn@4000000 {
|
|
compatible = "arm,ccn-504";
|
|
reg = <0x0 0x04000000 0x0 0x01000000>;
|
|
interrupts = <0 12 4>;
|
|
};
|
|
};
|
|
};
|