forked from Minki/linux
f228b494e5
The loop that browses the array compat_hwcap_str will stop when a NULL is encountered, however NULL is missing at the end of array. This will lead to overrun until a NULL is found somewhere in the following memory. In reality, this works out because the compat_hwcap2_str array tends to follow immediately in memory, and that *is* terminated correctly. Furthermore, the unsigned int compat_elf_hwcap is checked before printing each capability, so we end up doing the right thing because the size of the two arrays is less than 32. Still, this is an obvious mistake and should be fixed. Note for backporting: commit12d11817ea("arm64: Move /proc/cpuinfo handling code") moved this code in v4.4. Prior to that commit, the same change should be made in arch/arm64/kernel/setup.c. Fixes:44b82b7700"arm64: Fix up /proc/cpuinfo" Cc: <stable@vger.kernel.org> # v3.19+ (but see note above prior to v4.4) Signed-off-by: Julien Grall <julien.grall@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
261 lines
6.8 KiB
C
261 lines
6.8 KiB
C
/*
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* Record and handle CPU attributes.
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*
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* Copyright (C) 2014 ARM Ltd.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <asm/arch_timer.h>
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#include <asm/cachetype.h>
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#include <asm/cpu.h>
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#include <asm/cputype.h>
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#include <asm/cpufeature.h>
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#include <linux/bitops.h>
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#include <linux/bug.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/personality.h>
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#include <linux/preempt.h>
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#include <linux/printk.h>
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#include <linux/seq_file.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/delay.h>
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/*
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* In case the boot CPU is hotpluggable, we record its initial state and
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* current state separately. Certain system registers may contain different
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* values depending on configuration at or after reset.
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*/
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DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
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static struct cpuinfo_arm64 boot_cpu_data;
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static char *icache_policy_str[] = {
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[ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN",
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[ICACHE_POLICY_AIVIVT] = "AIVIVT",
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[ICACHE_POLICY_VIPT] = "VIPT",
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[ICACHE_POLICY_PIPT] = "PIPT",
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};
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unsigned long __icache_flags;
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static const char *const hwcap_str[] = {
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"fp",
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"asimd",
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"evtstrm",
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"aes",
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"pmull",
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"sha1",
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"sha2",
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"crc32",
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"atomics",
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"fphp",
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"asimdhp",
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NULL
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};
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#ifdef CONFIG_COMPAT
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static const char *const compat_hwcap_str[] = {
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"swp",
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"half",
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"thumb",
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"26bit",
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"fastmult",
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"fpa",
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"vfp",
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"edsp",
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"java",
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"iwmmxt",
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"crunch",
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"thumbee",
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"neon",
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"vfpv3",
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"vfpv3d16",
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"tls",
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"vfpv4",
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"idiva",
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"idivt",
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"vfpd32",
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"lpae",
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"evtstrm",
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NULL
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};
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static const char *const compat_hwcap2_str[] = {
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"aes",
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"pmull",
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"sha1",
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"sha2",
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"crc32",
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NULL
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};
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#endif /* CONFIG_COMPAT */
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static int c_show(struct seq_file *m, void *v)
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{
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int i, j;
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for_each_online_cpu(i) {
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struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
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u32 midr = cpuinfo->reg_midr;
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/*
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* glibc reads /proc/cpuinfo to determine the number of
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* online processors, looking for lines beginning with
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* "processor". Give glibc what it expects.
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*/
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seq_printf(m, "processor\t: %d\n", i);
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seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
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loops_per_jiffy / (500000UL/HZ),
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loops_per_jiffy / (5000UL/HZ) % 100);
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/*
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* Dump out the common processor features in a single line.
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* Userspace should read the hwcaps with getauxval(AT_HWCAP)
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* rather than attempting to parse this, but there's a body of
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* software which does already (at least for 32-bit).
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*/
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seq_puts(m, "Features\t:");
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if (personality(current->personality) == PER_LINUX32) {
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#ifdef CONFIG_COMPAT
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for (j = 0; compat_hwcap_str[j]; j++)
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if (compat_elf_hwcap & (1 << j))
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seq_printf(m, " %s", compat_hwcap_str[j]);
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for (j = 0; compat_hwcap2_str[j]; j++)
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if (compat_elf_hwcap2 & (1 << j))
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seq_printf(m, " %s", compat_hwcap2_str[j]);
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#endif /* CONFIG_COMPAT */
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} else {
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for (j = 0; hwcap_str[j]; j++)
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if (elf_hwcap & (1 << j))
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seq_printf(m, " %s", hwcap_str[j]);
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}
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seq_puts(m, "\n");
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seq_printf(m, "CPU implementer\t: 0x%02x\n",
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MIDR_IMPLEMENTOR(midr));
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seq_printf(m, "CPU architecture: 8\n");
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seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
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seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
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seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
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}
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return 0;
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}
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static void *c_start(struct seq_file *m, loff_t *pos)
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{
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return *pos < 1 ? (void *)1 : NULL;
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}
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static void *c_next(struct seq_file *m, void *v, loff_t *pos)
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{
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++*pos;
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return NULL;
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}
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static void c_stop(struct seq_file *m, void *v)
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{
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}
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const struct seq_operations cpuinfo_op = {
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.start = c_start,
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.next = c_next,
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.stop = c_stop,
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.show = c_show
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};
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static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
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{
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unsigned int cpu = smp_processor_id();
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u32 l1ip = CTR_L1IP(info->reg_ctr);
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if (l1ip != ICACHE_POLICY_PIPT) {
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/*
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* VIPT caches are non-aliasing if the VA always equals the PA
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* in all bit positions that are covered by the index. This is
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* the case if the size of a way (# of sets * line size) does
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* not exceed PAGE_SIZE.
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*/
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u32 waysize = icache_get_numsets() * icache_get_linesize();
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if (l1ip != ICACHE_POLICY_VIPT || waysize > PAGE_SIZE)
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set_bit(ICACHEF_ALIASING, &__icache_flags);
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}
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if (l1ip == ICACHE_POLICY_AIVIVT)
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set_bit(ICACHEF_AIVIVT, &__icache_flags);
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pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
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}
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static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
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{
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info->reg_cntfrq = arch_timer_get_cntfrq();
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info->reg_ctr = read_cpuid_cachetype();
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info->reg_dczid = read_cpuid(DCZID_EL0);
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info->reg_midr = read_cpuid_id();
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info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
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info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
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info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
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info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
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info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
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info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
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info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
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info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
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info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
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/* Update the 32bit ID registers only if AArch32 is implemented */
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if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
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info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
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info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
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info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
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info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
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info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
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info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
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info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
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info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
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info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
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info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
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info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
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info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
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info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
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info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
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info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
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info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
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}
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cpuinfo_detect_icache_policy(info);
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check_local_cpu_errata();
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}
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void cpuinfo_store_cpu(void)
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{
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struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
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__cpuinfo_store_cpu(info);
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update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
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}
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void __init cpuinfo_store_boot_cpu(void)
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{
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struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
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__cpuinfo_store_cpu(info);
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boot_cpu_data = *info;
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init_cpu_features(&boot_cpu_data);
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}
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