forked from Minki/linux
77fbdb30f0
The irq base offset needs to be ignored when matching irqs to external interrupt pins. Taking the offset into account resulted in the EIU not being brought up properly. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2616/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
325 lines
8.2 KiB
C
325 lines
8.2 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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* Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
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*/
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <asm/bootinfo.h>
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#include <asm/irq_cpu.h>
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#include <lantiq_soc.h>
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#include <irq.h>
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/* register definitions */
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#define LTQ_ICU_IM0_ISR 0x0000
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#define LTQ_ICU_IM0_IER 0x0008
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#define LTQ_ICU_IM0_IOSR 0x0010
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#define LTQ_ICU_IM0_IRSR 0x0018
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#define LTQ_ICU_IM0_IMR 0x0020
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#define LTQ_ICU_IM1_ISR 0x0028
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#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
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#define LTQ_EIU_EXIN_C 0x0000
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#define LTQ_EIU_EXIN_INIC 0x0004
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#define LTQ_EIU_EXIN_INEN 0x000C
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/* irq numbers used by the external interrupt unit (EIU) */
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#define LTQ_EIU_IR0 (INT_NUM_IM4_IRL0 + 30)
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#define LTQ_EIU_IR1 (INT_NUM_IM3_IRL0 + 31)
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#define LTQ_EIU_IR2 (INT_NUM_IM1_IRL0 + 26)
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#define LTQ_EIU_IR3 INT_NUM_IM1_IRL0
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#define LTQ_EIU_IR4 (INT_NUM_IM1_IRL0 + 1)
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#define LTQ_EIU_IR5 (INT_NUM_IM1_IRL0 + 2)
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#define LTQ_EIU_IR6 (INT_NUM_IM2_IRL0 + 30)
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#define MAX_EIU 6
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/* irqs generated by device attached to the EBU need to be acked in
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* a special manner
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*/
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#define LTQ_ICU_EBU_IRQ 22
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#define ltq_icu_w32(x, y) ltq_w32((x), ltq_icu_membase + (y))
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#define ltq_icu_r32(x) ltq_r32(ltq_icu_membase + (x))
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#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
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#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
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static unsigned short ltq_eiu_irq[MAX_EIU] = {
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LTQ_EIU_IR0,
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LTQ_EIU_IR1,
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LTQ_EIU_IR2,
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LTQ_EIU_IR3,
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LTQ_EIU_IR4,
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LTQ_EIU_IR5,
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};
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static struct resource ltq_icu_resource = {
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.name = "icu",
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.start = LTQ_ICU_BASE_ADDR,
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.end = LTQ_ICU_BASE_ADDR + LTQ_ICU_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct resource ltq_eiu_resource = {
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.name = "eiu",
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.start = LTQ_EIU_BASE_ADDR,
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.end = LTQ_EIU_BASE_ADDR + LTQ_ICU_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static void __iomem *ltq_icu_membase;
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static void __iomem *ltq_eiu_membase;
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void ltq_disable_irq(struct irq_data *d)
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{
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u32 ier = LTQ_ICU_IM0_IER;
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int irq_nr = d->irq - INT_NUM_IRQ0;
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ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
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irq_nr %= INT_NUM_IM_OFFSET;
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ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier);
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}
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void ltq_mask_and_ack_irq(struct irq_data *d)
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{
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u32 ier = LTQ_ICU_IM0_IER;
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u32 isr = LTQ_ICU_IM0_ISR;
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int irq_nr = d->irq - INT_NUM_IRQ0;
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ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
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isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
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irq_nr %= INT_NUM_IM_OFFSET;
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ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier);
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ltq_icu_w32((1 << irq_nr), isr);
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}
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static void ltq_ack_irq(struct irq_data *d)
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{
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u32 isr = LTQ_ICU_IM0_ISR;
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int irq_nr = d->irq - INT_NUM_IRQ0;
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isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
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irq_nr %= INT_NUM_IM_OFFSET;
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ltq_icu_w32((1 << irq_nr), isr);
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}
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void ltq_enable_irq(struct irq_data *d)
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{
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u32 ier = LTQ_ICU_IM0_IER;
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int irq_nr = d->irq - INT_NUM_IRQ0;
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ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
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irq_nr %= INT_NUM_IM_OFFSET;
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ltq_icu_w32(ltq_icu_r32(ier) | (1 << irq_nr), ier);
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}
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static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
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{
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int i;
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ltq_enable_irq(d);
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for (i = 0; i < MAX_EIU; i++) {
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if (d->irq == ltq_eiu_irq[i]) {
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/* low level - we should really handle set_type */
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ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
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(0x6 << (i * 4)), LTQ_EIU_EXIN_C);
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/* clear all pending */
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ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~(1 << i),
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LTQ_EIU_EXIN_INIC);
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/* enable */
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ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | (1 << i),
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LTQ_EIU_EXIN_INEN);
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break;
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}
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}
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return 0;
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}
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static void ltq_shutdown_eiu_irq(struct irq_data *d)
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{
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int i;
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ltq_disable_irq(d);
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for (i = 0; i < MAX_EIU; i++) {
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if (d->irq == ltq_eiu_irq[i]) {
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/* disable */
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ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~(1 << i),
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LTQ_EIU_EXIN_INEN);
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break;
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}
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}
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}
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static struct irq_chip ltq_irq_type = {
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"icu",
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.irq_enable = ltq_enable_irq,
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.irq_disable = ltq_disable_irq,
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.irq_unmask = ltq_enable_irq,
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.irq_ack = ltq_ack_irq,
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.irq_mask = ltq_disable_irq,
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.irq_mask_ack = ltq_mask_and_ack_irq,
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};
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static struct irq_chip ltq_eiu_type = {
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"eiu",
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.irq_startup = ltq_startup_eiu_irq,
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.irq_shutdown = ltq_shutdown_eiu_irq,
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.irq_enable = ltq_enable_irq,
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.irq_disable = ltq_disable_irq,
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.irq_unmask = ltq_enable_irq,
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.irq_ack = ltq_ack_irq,
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.irq_mask = ltq_disable_irq,
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.irq_mask_ack = ltq_mask_and_ack_irq,
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};
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static void ltq_hw_irqdispatch(int module)
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{
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u32 irq;
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irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR + (module * LTQ_ICU_OFFSET));
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if (irq == 0)
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return;
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/* silicon bug causes only the msb set to 1 to be valid. all
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* other bits might be bogus
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*/
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irq = __fls(irq);
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do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
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/* if this is a EBU irq, we need to ack it or get a deadlock */
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if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0))
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ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
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LTQ_EBU_PCC_ISTAT);
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}
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#define DEFINE_HWx_IRQDISPATCH(x) \
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static void ltq_hw ## x ## _irqdispatch(void) \
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{ \
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ltq_hw_irqdispatch(x); \
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}
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DEFINE_HWx_IRQDISPATCH(0)
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DEFINE_HWx_IRQDISPATCH(1)
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DEFINE_HWx_IRQDISPATCH(2)
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DEFINE_HWx_IRQDISPATCH(3)
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DEFINE_HWx_IRQDISPATCH(4)
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static void ltq_hw5_irqdispatch(void)
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{
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do_IRQ(MIPS_CPU_TIMER_IRQ);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
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unsigned int i;
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if (pending & CAUSEF_IP7) {
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do_IRQ(MIPS_CPU_TIMER_IRQ);
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goto out;
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} else {
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for (i = 0; i < 5; i++) {
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if (pending & (CAUSEF_IP2 << i)) {
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ltq_hw_irqdispatch(i);
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goto out;
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}
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}
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}
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pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
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out:
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return;
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}
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static struct irqaction cascade = {
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.handler = no_action,
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.flags = IRQF_DISABLED,
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.name = "cascade",
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};
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void __init arch_init_irq(void)
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{
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int i;
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if (insert_resource(&iomem_resource, <q_icu_resource) < 0)
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panic("Failed to insert icu memory\n");
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if (request_mem_region(ltq_icu_resource.start,
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resource_size(<q_icu_resource), "icu") < 0)
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panic("Failed to request icu memory\n");
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ltq_icu_membase = ioremap_nocache(ltq_icu_resource.start,
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resource_size(<q_icu_resource));
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if (!ltq_icu_membase)
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panic("Failed to remap icu memory\n");
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if (insert_resource(&iomem_resource, <q_eiu_resource) < 0)
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panic("Failed to insert eiu memory\n");
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if (request_mem_region(ltq_eiu_resource.start,
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resource_size(<q_eiu_resource), "eiu") < 0)
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panic("Failed to request eiu memory\n");
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ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start,
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resource_size(<q_eiu_resource));
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if (!ltq_eiu_membase)
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panic("Failed to remap eiu memory\n");
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/* make sure all irqs are turned off by default */
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for (i = 0; i < 5; i++)
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ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET));
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/* clear all possibly pending interrupts */
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ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));
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mips_cpu_irq_init();
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for (i = 2; i <= 6; i++)
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setup_irq(i, &cascade);
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if (cpu_has_vint) {
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pr_info("Setting up vectored interrupts\n");
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set_vi_handler(2, ltq_hw0_irqdispatch);
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set_vi_handler(3, ltq_hw1_irqdispatch);
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set_vi_handler(4, ltq_hw2_irqdispatch);
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set_vi_handler(5, ltq_hw3_irqdispatch);
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set_vi_handler(6, ltq_hw4_irqdispatch);
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set_vi_handler(7, ltq_hw5_irqdispatch);
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}
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for (i = INT_NUM_IRQ0;
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i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
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if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) ||
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(i == LTQ_EIU_IR2))
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irq_set_chip_and_handler(i, <q_eiu_type,
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handle_level_irq);
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/* EIU3-5 only exist on ar9 and vr9 */
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else if (((i == LTQ_EIU_IR3) || (i == LTQ_EIU_IR4) ||
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(i == LTQ_EIU_IR5)) && (ltq_is_ar9() || ltq_is_vr9()))
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irq_set_chip_and_handler(i, <q_eiu_type,
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handle_level_irq);
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else
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irq_set_chip_and_handler(i, <q_irq_type,
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handle_level_irq);
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#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
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set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
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IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
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#else
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set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
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IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
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#endif
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}
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unsigned int __cpuinit get_c0_compare_int(void)
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{
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return CP0_LEGACY_COMPARE_IRQ;
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}
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