f18b2f67ea
Add several missing RDMSRs for IDE and USB are missing to avoid the agressive modification of the high 32 bits of the MSR. Without this patch some usb devices may fail after printing "reset ehci host ....." when reading the partition information. Signed-off-by: Hu Hongbing <huhb@lemote.com> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: Zhang Le <r0bertz@gentoo.org> Cc: Hu Hongbing <huhb@lemote.com> Patchwork: http://patchwork.linux-mips.org/patch/1250/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
192 lines
4.8 KiB
C
192 lines
4.8 KiB
C
/*
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* the IDE Virtual Support Module of AMD CS5536
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*
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* Copyright (C) 2007 Lemote, Inc.
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* Author : jlliu, liujl@lemote.com
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*
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* Copyright (C) 2009 Lemote, Inc.
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* Author: Wu Zhangjin, wuzhangjin@gmail.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <cs5536/cs5536.h>
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#include <cs5536/cs5536_pci.h>
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void pci_ide_write_reg(int reg, u32 value)
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{
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u32 hi = 0, lo = value;
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switch (reg) {
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case PCI_COMMAND:
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_rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
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if (value & PCI_COMMAND_MASTER)
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lo |= (0x03 << 4);
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else
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lo &= ~(0x03 << 4);
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_wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
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break;
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case PCI_STATUS:
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if (value & PCI_STATUS_PARITY) {
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_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
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if (lo & SB_PARE_ERR_FLAG) {
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lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
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_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
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}
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}
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break;
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case PCI_CACHE_LINE_SIZE:
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value &= 0x0000ff00;
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_rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
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hi &= 0xffffff00;
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hi |= (value >> 8);
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_wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
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break;
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case PCI_BAR4_REG:
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if (value == PCI_BAR_RANGE_MASK) {
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_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
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lo |= SOFT_BAR_IDE_FLAG;
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_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
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} else if (value & 0x01) {
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_rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
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lo = (value & 0xfffffff0) | 0x1;
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_wrmsr(IDE_MSR_REG(IDE_IO_BAR), hi, lo);
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value &= 0xfffffffc;
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hi = 0x60000000 | ((value & 0x000ff000) >> 12);
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lo = 0x000ffff0 | ((value & 0x00000fff) << 20);
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_wrmsr(GLIU_MSR_REG(GLIU_IOD_BM2), hi, lo);
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}
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break;
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case PCI_IDE_CFG_REG:
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if (value == CS5536_IDE_FLASH_SIGNATURE) {
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_rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo);
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lo |= 0x01;
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_wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo);
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} else {
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_rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo);
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lo = value;
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_wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo);
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}
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break;
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case PCI_IDE_DTC_REG:
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_rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo);
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lo = value;
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_wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo);
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break;
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case PCI_IDE_CAST_REG:
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_rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo);
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lo = value;
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_wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo);
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break;
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case PCI_IDE_ETC_REG:
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_rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo);
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lo = value;
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_wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo);
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break;
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case PCI_IDE_PM_REG:
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_rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo);
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lo = value;
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_wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo);
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break;
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default:
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break;
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}
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}
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u32 pci_ide_read_reg(int reg)
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{
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u32 conf_data = 0;
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u32 hi, lo;
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switch (reg) {
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case PCI_VENDOR_ID:
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conf_data =
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CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, CS5536_VENDOR_ID);
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break;
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case PCI_COMMAND:
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_rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
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if (lo & 0xfffffff0)
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conf_data |= PCI_COMMAND_IO;
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_rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
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if ((lo & 0x30) == 0x30)
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conf_data |= PCI_COMMAND_MASTER;
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break;
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case PCI_STATUS:
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conf_data |= PCI_STATUS_66MHZ;
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conf_data |= PCI_STATUS_FAST_BACK;
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_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
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if (lo & SB_PARE_ERR_FLAG)
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conf_data |= PCI_STATUS_PARITY;
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conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
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break;
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case PCI_CLASS_REVISION:
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_rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo);
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conf_data = lo & 0x000000ff;
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conf_data |= (CS5536_IDE_CLASS_CODE << 8);
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break;
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case PCI_CACHE_LINE_SIZE:
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_rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
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hi &= 0x000000f8;
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conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi);
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break;
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case PCI_BAR4_REG:
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_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
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if (lo & SOFT_BAR_IDE_FLAG) {
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conf_data = CS5536_IDE_RANGE |
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PCI_BASE_ADDRESS_SPACE_IO;
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lo &= ~SOFT_BAR_IDE_FLAG;
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_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
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} else {
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_rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
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conf_data = lo & 0xfffffff0;
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conf_data |= 0x01;
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conf_data &= ~0x02;
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}
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break;
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case PCI_CARDBUS_CIS:
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conf_data = PCI_CARDBUS_CIS_POINTER;
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break;
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case PCI_SUBSYSTEM_VENDOR_ID:
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conf_data =
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CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, CS5536_SUB_VENDOR_ID);
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break;
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case PCI_ROM_ADDRESS:
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conf_data = PCI_EXPANSION_ROM_BAR;
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break;
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case PCI_CAPABILITY_LIST:
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conf_data = PCI_CAPLIST_POINTER;
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break;
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case PCI_INTERRUPT_LINE:
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conf_data =
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CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR);
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break;
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case PCI_IDE_CFG_REG:
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_rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo);
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conf_data = lo;
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break;
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case PCI_IDE_DTC_REG:
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_rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo);
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conf_data = lo;
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break;
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case PCI_IDE_CAST_REG:
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_rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo);
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conf_data = lo;
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break;
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case PCI_IDE_ETC_REG:
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_rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo);
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conf_data = lo;
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case PCI_IDE_PM_REG:
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_rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo);
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conf_data = lo;
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break;
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default:
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break;
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}
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return conf_data;
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}
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