forked from Minki/linux
463873d570
Since we have no MMU, the kernel needs to validate that the submitted shader code won't make any accesses to memory that the user doesn't control, which involves banning some operations (general purpose DMA writes), and tracking where we need to write out pointers for other operations (texture sampling). Once it's validated, we return a GEM BO containing the shader, which doesn't allow mapping for write or exporting to other subsystems. v2: Use __u32-style types. Signed-off-by: Eric Anholt <eric@anholt.net>
265 lines
6.4 KiB
C
265 lines
6.4 KiB
C
/*
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* Copyright © 2014 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef VC4_QPU_DEFINES_H
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#define VC4_QPU_DEFINES_H
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enum qpu_op_add {
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QPU_A_NOP,
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QPU_A_FADD,
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QPU_A_FSUB,
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QPU_A_FMIN,
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QPU_A_FMAX,
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QPU_A_FMINABS,
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QPU_A_FMAXABS,
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QPU_A_FTOI,
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QPU_A_ITOF,
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QPU_A_ADD = 12,
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QPU_A_SUB,
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QPU_A_SHR,
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QPU_A_ASR,
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QPU_A_ROR,
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QPU_A_SHL,
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QPU_A_MIN,
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QPU_A_MAX,
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QPU_A_AND,
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QPU_A_OR,
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QPU_A_XOR,
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QPU_A_NOT,
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QPU_A_CLZ,
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QPU_A_V8ADDS = 30,
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QPU_A_V8SUBS = 31,
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};
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enum qpu_op_mul {
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QPU_M_NOP,
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QPU_M_FMUL,
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QPU_M_MUL24,
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QPU_M_V8MULD,
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QPU_M_V8MIN,
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QPU_M_V8MAX,
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QPU_M_V8ADDS,
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QPU_M_V8SUBS,
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};
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enum qpu_raddr {
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QPU_R_FRAG_PAYLOAD_ZW = 15, /* W for A file, Z for B file */
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/* 0-31 are the plain regfile a or b fields */
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QPU_R_UNIF = 32,
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QPU_R_VARY = 35,
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QPU_R_ELEM_QPU = 38,
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QPU_R_NOP,
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QPU_R_XY_PIXEL_COORD = 41,
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QPU_R_MS_REV_FLAGS = 41,
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QPU_R_VPM = 48,
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QPU_R_VPM_LD_BUSY,
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QPU_R_VPM_LD_WAIT,
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QPU_R_MUTEX_ACQUIRE,
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};
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enum qpu_waddr {
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/* 0-31 are the plain regfile a or b fields */
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QPU_W_ACC0 = 32, /* aka r0 */
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QPU_W_ACC1,
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QPU_W_ACC2,
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QPU_W_ACC3,
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QPU_W_TMU_NOSWAP,
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QPU_W_ACC5,
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QPU_W_HOST_INT,
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QPU_W_NOP,
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QPU_W_UNIFORMS_ADDRESS,
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QPU_W_QUAD_XY, /* X for regfile a, Y for regfile b */
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QPU_W_MS_FLAGS = 42,
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QPU_W_REV_FLAG = 42,
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QPU_W_TLB_STENCIL_SETUP = 43,
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QPU_W_TLB_Z,
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QPU_W_TLB_COLOR_MS,
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QPU_W_TLB_COLOR_ALL,
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QPU_W_TLB_ALPHA_MASK,
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QPU_W_VPM,
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QPU_W_VPMVCD_SETUP, /* LD for regfile a, ST for regfile b */
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QPU_W_VPM_ADDR, /* LD for regfile a, ST for regfile b */
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QPU_W_MUTEX_RELEASE,
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QPU_W_SFU_RECIP,
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QPU_W_SFU_RECIPSQRT,
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QPU_W_SFU_EXP,
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QPU_W_SFU_LOG,
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QPU_W_TMU0_S,
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QPU_W_TMU0_T,
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QPU_W_TMU0_R,
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QPU_W_TMU0_B,
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QPU_W_TMU1_S,
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QPU_W_TMU1_T,
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QPU_W_TMU1_R,
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QPU_W_TMU1_B,
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};
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enum qpu_sig_bits {
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QPU_SIG_SW_BREAKPOINT,
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QPU_SIG_NONE,
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QPU_SIG_THREAD_SWITCH,
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QPU_SIG_PROG_END,
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QPU_SIG_WAIT_FOR_SCOREBOARD,
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QPU_SIG_SCOREBOARD_UNLOCK,
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QPU_SIG_LAST_THREAD_SWITCH,
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QPU_SIG_COVERAGE_LOAD,
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QPU_SIG_COLOR_LOAD,
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QPU_SIG_COLOR_LOAD_END,
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QPU_SIG_LOAD_TMU0,
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QPU_SIG_LOAD_TMU1,
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QPU_SIG_ALPHA_MASK_LOAD,
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QPU_SIG_SMALL_IMM,
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QPU_SIG_LOAD_IMM,
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QPU_SIG_BRANCH
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};
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enum qpu_mux {
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/* hardware mux values */
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QPU_MUX_R0,
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QPU_MUX_R1,
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QPU_MUX_R2,
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QPU_MUX_R3,
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QPU_MUX_R4,
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QPU_MUX_R5,
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QPU_MUX_A,
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QPU_MUX_B,
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/* non-hardware mux values */
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QPU_MUX_IMM,
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};
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enum qpu_cond {
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QPU_COND_NEVER,
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QPU_COND_ALWAYS,
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QPU_COND_ZS,
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QPU_COND_ZC,
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QPU_COND_NS,
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QPU_COND_NC,
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QPU_COND_CS,
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QPU_COND_CC,
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};
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enum qpu_pack_mul {
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QPU_PACK_MUL_NOP,
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/* replicated to each 8 bits of the 32-bit dst. */
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QPU_PACK_MUL_8888 = 3,
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QPU_PACK_MUL_8A,
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QPU_PACK_MUL_8B,
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QPU_PACK_MUL_8C,
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QPU_PACK_MUL_8D,
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};
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enum qpu_pack_a {
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QPU_PACK_A_NOP,
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/* convert to 16 bit float if float input, or to int16. */
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QPU_PACK_A_16A,
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QPU_PACK_A_16B,
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/* replicated to each 8 bits of the 32-bit dst. */
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QPU_PACK_A_8888,
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/* Convert to 8-bit unsigned int. */
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QPU_PACK_A_8A,
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QPU_PACK_A_8B,
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QPU_PACK_A_8C,
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QPU_PACK_A_8D,
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/* Saturating variants of the previous instructions. */
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QPU_PACK_A_32_SAT, /* int-only */
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QPU_PACK_A_16A_SAT, /* int or float */
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QPU_PACK_A_16B_SAT,
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QPU_PACK_A_8888_SAT,
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QPU_PACK_A_8A_SAT,
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QPU_PACK_A_8B_SAT,
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QPU_PACK_A_8C_SAT,
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QPU_PACK_A_8D_SAT,
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};
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enum qpu_unpack_r4 {
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QPU_UNPACK_R4_NOP,
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QPU_UNPACK_R4_F16A_TO_F32,
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QPU_UNPACK_R4_F16B_TO_F32,
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QPU_UNPACK_R4_8D_REP,
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QPU_UNPACK_R4_8A,
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QPU_UNPACK_R4_8B,
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QPU_UNPACK_R4_8C,
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QPU_UNPACK_R4_8D,
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};
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#define QPU_MASK(high, low) \
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((((uint64_t)1 << ((high) - (low) + 1)) - 1) << (low))
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#define QPU_GET_FIELD(word, field) \
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((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT))
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#define QPU_SIG_SHIFT 60
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#define QPU_SIG_MASK QPU_MASK(63, 60)
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#define QPU_UNPACK_SHIFT 57
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#define QPU_UNPACK_MASK QPU_MASK(59, 57)
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/**
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* If set, the pack field means PACK_MUL or R4 packing, instead of normal
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* regfile a packing.
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*/
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#define QPU_PM ((uint64_t)1 << 56)
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#define QPU_PACK_SHIFT 52
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#define QPU_PACK_MASK QPU_MASK(55, 52)
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#define QPU_COND_ADD_SHIFT 49
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#define QPU_COND_ADD_MASK QPU_MASK(51, 49)
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#define QPU_COND_MUL_SHIFT 46
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#define QPU_COND_MUL_MASK QPU_MASK(48, 46)
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#define QPU_SF ((uint64_t)1 << 45)
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#define QPU_WADDR_ADD_SHIFT 38
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#define QPU_WADDR_ADD_MASK QPU_MASK(43, 38)
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#define QPU_WADDR_MUL_SHIFT 32
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#define QPU_WADDR_MUL_MASK QPU_MASK(37, 32)
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#define QPU_OP_MUL_SHIFT 29
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#define QPU_OP_MUL_MASK QPU_MASK(31, 29)
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#define QPU_RADDR_A_SHIFT 18
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#define QPU_RADDR_A_MASK QPU_MASK(23, 18)
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#define QPU_RADDR_B_SHIFT 12
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#define QPU_RADDR_B_MASK QPU_MASK(17, 12)
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#define QPU_SMALL_IMM_SHIFT 12
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#define QPU_SMALL_IMM_MASK QPU_MASK(17, 12)
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#define QPU_ADD_A_SHIFT 9
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#define QPU_ADD_A_MASK QPU_MASK(11, 9)
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#define QPU_ADD_B_SHIFT 6
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#define QPU_ADD_B_MASK QPU_MASK(8, 6)
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#define QPU_MUL_A_SHIFT 3
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#define QPU_MUL_A_MASK QPU_MASK(5, 3)
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#define QPU_MUL_B_SHIFT 0
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#define QPU_MUL_B_MASK QPU_MASK(2, 0)
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#define QPU_WS ((uint64_t)1 << 44)
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#define QPU_OP_ADD_SHIFT 24
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#define QPU_OP_ADD_MASK QPU_MASK(28, 24)
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#endif /* VC4_QPU_DEFINES_H */
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