f0c7bf1b77
OpenRISC is the only architecture which uses asm-generic/atomic.h and also provides its own implementation of some functions, requiring ifdeferry in the asm-generic header. As OpenRISC provides the vast majority of functions itself, it would be simpler overall if it also provided the few functions it cribs from asm-generic. This patch decouples OpenRISC from asm-generic/atomic.h. Subsequent patches will simplify the asm-generic implementation and remove the now unnecessary ifdeferry. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Stafford Horne <shorne@gmail.com> Cc: Boqun Feng <boqun.feng@gmail.com> Cc: Jonas Bonn <jonas@southpole.se> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> Cc: Will Deacon <will@kernel.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20210525140232.53872-6-mark.rutland@arm.com
133 lines
3.3 KiB
C
133 lines
3.3 KiB
C
/*
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* Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#ifndef __ASM_OPENRISC_ATOMIC_H
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#define __ASM_OPENRISC_ATOMIC_H
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#include <linux/types.h>
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/* Atomically perform op with v->counter and i */
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#define ATOMIC_OP(op) \
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static inline void atomic_##op(int i, atomic_t *v) \
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{ \
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int tmp; \
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\
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__asm__ __volatile__( \
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"1: l.lwa %0,0(%1) \n" \
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" l." #op " %0,%0,%2 \n" \
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" l.swa 0(%1),%0 \n" \
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" l.bnf 1b \n" \
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" l.nop \n" \
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: "=&r"(tmp) \
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: "r"(&v->counter), "r"(i) \
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: "cc", "memory"); \
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}
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/* Atomically perform op with v->counter and i, return the result */
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#define ATOMIC_OP_RETURN(op) \
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static inline int atomic_##op##_return(int i, atomic_t *v) \
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{ \
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int tmp; \
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\
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__asm__ __volatile__( \
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"1: l.lwa %0,0(%1) \n" \
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" l." #op " %0,%0,%2 \n" \
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" l.swa 0(%1),%0 \n" \
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" l.bnf 1b \n" \
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" l.nop \n" \
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: "=&r"(tmp) \
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: "r"(&v->counter), "r"(i) \
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: "cc", "memory"); \
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\
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return tmp; \
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}
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/* Atomically perform op with v->counter and i, return orig v->counter */
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#define ATOMIC_FETCH_OP(op) \
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static inline int atomic_fetch_##op(int i, atomic_t *v) \
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{ \
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int tmp, old; \
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\
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__asm__ __volatile__( \
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"1: l.lwa %0,0(%2) \n" \
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" l." #op " %1,%0,%3 \n" \
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" l.swa 0(%2),%1 \n" \
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" l.bnf 1b \n" \
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" l.nop \n" \
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: "=&r"(old), "=&r"(tmp) \
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: "r"(&v->counter), "r"(i) \
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: "cc", "memory"); \
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\
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return old; \
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}
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ATOMIC_OP_RETURN(add)
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ATOMIC_OP_RETURN(sub)
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ATOMIC_FETCH_OP(add)
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ATOMIC_FETCH_OP(sub)
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ATOMIC_FETCH_OP(and)
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ATOMIC_FETCH_OP(or)
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ATOMIC_FETCH_OP(xor)
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ATOMIC_OP(and)
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ATOMIC_OP(or)
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ATOMIC_OP(xor)
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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#define atomic_add_return atomic_add_return
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#define atomic_sub_return atomic_sub_return
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#define atomic_fetch_add atomic_fetch_add
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#define atomic_fetch_sub atomic_fetch_sub
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#define atomic_fetch_and atomic_fetch_and
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#define atomic_fetch_or atomic_fetch_or
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#define atomic_fetch_xor atomic_fetch_xor
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#define atomic_and atomic_and
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#define atomic_or atomic_or
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#define atomic_xor atomic_xor
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/*
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* Atomically add a to v->counter as long as v is not already u.
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* Returns the original value at v->counter.
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*
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* This is often used through atomic_inc_not_zero()
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*/
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static inline int atomic_fetch_add_unless(atomic_t *v, int a, int u)
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{
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int old, tmp;
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__asm__ __volatile__(
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"1: l.lwa %0, 0(%2) \n"
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" l.sfeq %0, %4 \n"
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" l.bf 2f \n"
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" l.add %1, %0, %3 \n"
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" l.swa 0(%2), %1 \n"
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" l.bnf 1b \n"
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" l.nop \n"
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"2: \n"
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: "=&r"(old), "=&r" (tmp)
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: "r"(&v->counter), "r"(a), "r"(u)
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: "cc", "memory");
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return old;
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}
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#define atomic_fetch_add_unless atomic_fetch_add_unless
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#define atomic_read(v) READ_ONCE((v)->counter)
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#define atomic_set(v,i) WRITE_ONCE((v)->counter, (i))
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#include <asm/cmpxchg.h>
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#define atomic_xchg(ptr, v) (xchg(&(ptr)->counter, (v)))
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#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), (old), (new)))
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#endif /* __ASM_OPENRISC_ATOMIC_H */
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