forked from Minki/linux
509eb76ebf
__my_cpu_offset is non-volatile, since we want its value to be cached
when we access several per-cpu variables in a row with preemption
disabled. This means that we rely on preempt_{en,dis}able to hazard
with the operation via the barrier() macro, so that we can't end up
migrating CPUs without reloading the per-cpu offset.
Unfortunately, GCC doesn't treat a "memory" clobber on a non-volatile
asm block as a side-effect, and will happily re-order it before other
memory clobbers (including those in prempt_disable()) and cache the
value. This has been observed to break the cmpxchg logic in the slub
allocator, leading to livelock in kmem_cache_alloc in mainline kernels.
This patch adds a dummy memory input operand to __my_cpu_offset,
forcing it to be ordered with respect to the barrier() macro.
Cc: <stable@vger.kernel.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
53 lines
1.5 KiB
C
53 lines
1.5 KiB
C
/*
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* Copyright 2012 Calxeda, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _ASM_ARM_PERCPU_H_
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#define _ASM_ARM_PERCPU_H_
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/*
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* Same as asm-generic/percpu.h, except that we store the per cpu offset
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* in the TPIDRPRW. TPIDRPRW only exists on V6K and V7
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*/
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#if defined(CONFIG_SMP) && !defined(CONFIG_CPU_V6)
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static inline void set_my_cpu_offset(unsigned long off)
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{
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/* Set TPIDRPRW */
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asm volatile("mcr p15, 0, %0, c13, c0, 4" : : "r" (off) : "memory");
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}
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static inline unsigned long __my_cpu_offset(void)
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{
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unsigned long off;
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register unsigned long *sp asm ("sp");
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/*
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* Read TPIDRPRW.
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* We want to allow caching the value, so avoid using volatile and
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* instead use a fake stack read to hazard against barrier().
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*/
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asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) : "Q" (*sp));
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return off;
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}
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#define __my_cpu_offset __my_cpu_offset()
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#else
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#define set_my_cpu_offset(x) do {} while(0)
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#endif /* CONFIG_SMP */
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#include <asm-generic/percpu.h>
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#endif /* _ASM_ARM_PERCPU_H_ */
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