forked from Minki/linux
83ed90155f
Which means that iwl-io.c doesn't need to include iwl-dev.h any more. Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
223 lines
7.1 KiB
C
223 lines
7.1 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
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*
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* Portions of this file are derived from the ipw3945 project, as well
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* as portions of the ieee80211 subsystem header files.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* Intel Linux Wireless <ilw@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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*****************************************************************************/
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#ifndef __iwl_trans_int_pcie_h__
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#define __iwl_trans_int_pcie_h__
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/skbuff.h>
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#include "iwl-fh.h"
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#include "iwl-csr.h"
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#include "iwl-shared.h"
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#include "iwl-trans.h"
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#include "iwl-debug.h"
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#include "iwl-io.h"
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struct iwl_tx_queue;
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struct iwl_queue;
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struct iwl_host_cmd;
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/*This file includes the declaration that are internal to the
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* trans_pcie layer */
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/**
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* struct isr_statistics - interrupt statistics
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*
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*/
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struct isr_statistics {
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u32 hw;
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u32 sw;
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u32 err_code;
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u32 sch;
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u32 alive;
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u32 rfkill;
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u32 ctkill;
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u32 wakeup;
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u32 rx;
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u32 tx;
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u32 unhandled;
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};
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/**
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* struct iwl_rx_queue - Rx queue
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* @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
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* @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
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* @pool:
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* @queue:
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* @read: Shared index to newest available Rx buffer
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* @write: Shared index to oldest written Rx packet
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* @free_count: Number of pre-allocated buffers in rx_free
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* @write_actual:
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* @rx_free: list of free SKBs for use
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* @rx_used: List of Rx buffers with no SKB
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* @need_update: flag to indicate we need to update read/write index
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* @rb_stts: driver's pointer to receive buffer status
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* @rb_stts_dma: bus address of receive buffer status
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* @lock:
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*
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* NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
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*/
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struct iwl_rx_queue {
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__le32 *bd;
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dma_addr_t bd_dma;
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struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
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struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
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u32 read;
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u32 write;
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u32 free_count;
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u32 write_actual;
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struct list_head rx_free;
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struct list_head rx_used;
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int need_update;
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struct iwl_rb_status *rb_stts;
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dma_addr_t rb_stts_dma;
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spinlock_t lock;
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};
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struct iwl_dma_ptr {
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dma_addr_t dma;
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void *addr;
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size_t size;
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};
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/**
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* struct iwl_trans_pcie - PCIe transport specific data
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* @rxq: all the RX queue data
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* @rx_replenish: work that will be called when buffers need to be allocated
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* @trans: pointer to the generic transport area
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* @scd_base_addr: scheduler sram base address in SRAM
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* @scd_bc_tbls: pointer to the byte count table of the scheduler
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* @kw: keep warm address
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*/
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struct iwl_trans_pcie {
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struct iwl_rx_queue rxq;
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struct work_struct rx_replenish;
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struct iwl_trans *trans;
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/* INT ICT Table */
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__le32 *ict_tbl;
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void *ict_tbl_vir;
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dma_addr_t ict_tbl_dma;
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dma_addr_t aligned_ict_tbl_dma;
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int ict_index;
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u32 inta;
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bool use_ict;
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struct tasklet_struct irq_tasklet;
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struct isr_statistics isr_stats;
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u32 inta_mask;
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u32 scd_base_addr;
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struct iwl_dma_ptr scd_bc_tbls;
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struct iwl_dma_ptr kw;
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};
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#define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
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((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))
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/*****************************************************
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* RX
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******************************************************/
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void iwl_bg_rx_replenish(struct work_struct *data);
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void iwl_irq_tasklet(struct iwl_trans *trans);
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void iwlagn_rx_replenish(struct iwl_trans *trans);
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void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
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struct iwl_rx_queue *q);
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/*****************************************************
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* ICT
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******************************************************/
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int iwl_reset_ict(struct iwl_trans *trans);
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void iwl_disable_ict(struct iwl_trans *trans);
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int iwl_alloc_isr_ict(struct iwl_trans *trans);
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void iwl_free_isr_ict(struct iwl_trans *trans);
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irqreturn_t iwl_isr_ict(int irq, void *data);
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/*****************************************************
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* TX / HCMD
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******************************************************/
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void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq);
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int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
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struct iwl_tx_queue *txq,
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dma_addr_t addr, u16 len, u8 reset);
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int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id);
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int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
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int __must_check iwl_trans_pcie_send_cmd_pdu(struct iwl_trans *trans, u8 id,
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u32 flags, u16 len, const void *data);
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void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb);
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void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
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struct iwl_tx_queue *txq,
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u16 byte_cnt);
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int iwl_trans_pcie_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
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u16 ssn_idx, u8 tx_fifo);
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void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, int txq_id, u32 index);
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void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
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struct iwl_tx_queue *txq,
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int tx_fifo_id, int scd_retry);
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void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv, int sta_id, int tid,
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int frame_limit);
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void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
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int index);
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void iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
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struct sk_buff_head *skbs);
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/*****************************************************
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* Error handling
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******************************************************/
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int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
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char **buf, bool display);
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int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display);
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void iwl_dump_csr(struct iwl_trans *trans);
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static inline void iwl_disable_interrupts(struct iwl_trans *trans)
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{
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clear_bit(STATUS_INT_ENABLED, &trans->shrd->status);
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/* disable interrupts from uCode/NIC to host */
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iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
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/* acknowledge/clear/reset any interrupts still pending
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* from uCode or flow handler (Rx/Tx DMA) */
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iwl_write32(bus(trans), CSR_INT, 0xffffffff);
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iwl_write32(bus(trans), CSR_FH_INT_STATUS, 0xffffffff);
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IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
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}
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static inline void iwl_enable_interrupts(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie =
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IWL_TRANS_GET_PCIE_TRANS(trans);
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IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
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set_bit(STATUS_INT_ENABLED, &trans->shrd->status);
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iwl_write32(bus(trans), CSR_INT_MASK, trans_pcie->inta_mask);
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}
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#endif /* __iwl_trans_int_pcie_h__ */
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