ed57cac83e
The main idea behind randomising the EL2 VA is that we usually have a few spare bits between the most significant bit of the VA mask and the most significant bit of the linear mapping. Those bits could be a bunch of zeroes, and could be useful to move things around a bit. Of course, the more memory you have, the less randomisation you get... Alternatively, these bits could be the result of KASLR, in which case they are already random. But it would be nice to have a *different* randomization, just to make the job of a potential attacker a bit more difficult. Inserting these random bits is a bit involved. We don't have a spare register (short of rewriting all the kern_hyp_va call sites), and the immediate we want to insert is too random to be used with the ORR instruction. The best option I could come up with is the following sequence: and x0, x0, #va_mask ror x0, x0, #first_random_bit add x0, x0, #(random & 0xfff) add x0, x0, #(random >> 12), lsl #12 ror x0, x0, #(63 - first_random_bit) making it a fairly long sequence, but one that a decent CPU should be able to execute without breaking a sweat. It is of course NOPed out on VHE. The last 4 instructions can also be turned into NOPs if it appears that there is no free bits to use. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: James Morse <james.morse@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
153 lines
4.0 KiB
C
153 lines
4.0 KiB
C
/*
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* Copyright (C) 2017 ARM Ltd.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kvm_host.h>
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#include <linux/random.h>
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#include <linux/memblock.h>
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#include <asm/alternative.h>
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#include <asm/debug-monitors.h>
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#include <asm/insn.h>
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#include <asm/kvm_mmu.h>
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/*
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* The LSB of the random hyp VA tag or 0 if no randomization is used.
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*/
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static u8 tag_lsb;
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/*
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* The random hyp VA tag value with the region bit if hyp randomization is used
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*/
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static u64 tag_val;
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static u64 va_mask;
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static void compute_layout(void)
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{
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phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
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u64 hyp_va_msb;
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int kva_msb;
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/* Where is my RAM region? */
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hyp_va_msb = idmap_addr & BIT(VA_BITS - 1);
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hyp_va_msb ^= BIT(VA_BITS - 1);
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kva_msb = fls64((u64)phys_to_virt(memblock_start_of_DRAM()) ^
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(u64)(high_memory - 1));
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if (kva_msb == (VA_BITS - 1)) {
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/*
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* No space in the address, let's compute the mask so
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* that it covers (VA_BITS - 1) bits, and the region
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* bit. The tag stays set to zero.
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*/
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va_mask = BIT(VA_BITS - 1) - 1;
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va_mask |= hyp_va_msb;
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} else {
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/*
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* We do have some free bits to insert a random tag.
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* Hyp VAs are now created from kernel linear map VAs
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* using the following formula (with V == VA_BITS):
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*
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* 63 ... V | V-1 | V-2 .. tag_lsb | tag_lsb - 1 .. 0
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* ---------------------------------------------------------
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* | 0000000 | hyp_va_msb | random tag | kern linear VA |
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*/
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tag_lsb = kva_msb;
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va_mask = GENMASK_ULL(tag_lsb - 1, 0);
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tag_val = get_random_long() & GENMASK_ULL(VA_BITS - 2, tag_lsb);
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tag_val |= hyp_va_msb;
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tag_val >>= tag_lsb;
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}
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}
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static u32 compute_instruction(int n, u32 rd, u32 rn)
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{
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u32 insn = AARCH64_BREAK_FAULT;
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switch (n) {
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case 0:
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insn = aarch64_insn_gen_logical_immediate(AARCH64_INSN_LOGIC_AND,
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AARCH64_INSN_VARIANT_64BIT,
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rn, rd, va_mask);
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break;
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case 1:
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/* ROR is a variant of EXTR with Rm = Rn */
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insn = aarch64_insn_gen_extr(AARCH64_INSN_VARIANT_64BIT,
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rn, rn, rd,
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tag_lsb);
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break;
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case 2:
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insn = aarch64_insn_gen_add_sub_imm(rd, rn,
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tag_val & GENMASK(11, 0),
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AARCH64_INSN_VARIANT_64BIT,
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AARCH64_INSN_ADSB_ADD);
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break;
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case 3:
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insn = aarch64_insn_gen_add_sub_imm(rd, rn,
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tag_val & GENMASK(23, 12),
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AARCH64_INSN_VARIANT_64BIT,
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AARCH64_INSN_ADSB_ADD);
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break;
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case 4:
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/* ROR is a variant of EXTR with Rm = Rn */
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insn = aarch64_insn_gen_extr(AARCH64_INSN_VARIANT_64BIT,
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rn, rn, rd, 64 - tag_lsb);
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break;
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}
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return insn;
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}
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void __init kvm_update_va_mask(struct alt_instr *alt,
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__le32 *origptr, __le32 *updptr, int nr_inst)
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{
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int i;
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BUG_ON(nr_inst != 5);
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if (!has_vhe() && !va_mask)
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compute_layout();
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for (i = 0; i < nr_inst; i++) {
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u32 rd, rn, insn, oinsn;
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/*
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* VHE doesn't need any address translation, let's NOP
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* everything.
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*
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* Alternatively, if we don't have any spare bits in
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* the address, NOP everything after masking that
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* kernel VA.
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*/
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if (has_vhe() || (!tag_lsb && i > 0)) {
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updptr[i] = cpu_to_le32(aarch64_insn_gen_nop());
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continue;
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}
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oinsn = le32_to_cpu(origptr[i]);
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rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, oinsn);
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rn = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, oinsn);
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insn = compute_instruction(i, rd, rn);
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BUG_ON(insn == AARCH64_BREAK_FAULT);
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updptr[i] = cpu_to_le32(insn);
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}
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}
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