262 lines
7.0 KiB
C
262 lines
7.0 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "priv.h"
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#include <core/gpuobj.h>
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#include <subdev/fb.h>
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#include <subdev/mmu.h>
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#include <subdev/timer.h>
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struct nv50_bar {
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struct nvkm_bar base;
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spinlock_t lock;
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struct nvkm_gpuobj *mem;
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struct nvkm_gpuobj *pad;
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struct nvkm_gpuobj *pgd;
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struct nvkm_vm *bar1_vm;
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struct nvkm_gpuobj *bar1;
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struct nvkm_vm *bar3_vm;
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struct nvkm_gpuobj *bar3;
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};
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static struct nvkm_vm *
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nv50_bar_kmap(struct nvkm_bar *obj)
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{
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struct nv50_bar *bar = container_of(obj, typeof(*bar), base);
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return bar->bar3_vm;
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}
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static int
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nv50_bar_umap(struct nvkm_bar *obj, u64 size, int type, struct nvkm_vma *vma)
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{
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struct nv50_bar *bar = container_of(obj, typeof(*bar), base);
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return nvkm_vm_get(bar->bar1_vm, size, type, NV_MEM_ACCESS_RW, vma);
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}
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static void
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nv50_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma)
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{
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nvkm_vm_unmap(vma);
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nvkm_vm_put(vma);
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}
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static void
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nv50_bar_flush(struct nvkm_bar *obj)
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{
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struct nv50_bar *bar = container_of(obj, typeof(*bar), base);
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struct nvkm_device *device = bar->base.subdev.device;
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unsigned long flags;
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spin_lock_irqsave(&bar->lock, flags);
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nvkm_wr32(device, 0x00330c, 0x00000001);
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nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, 0x00330c) & 0x00000002))
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break;
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);
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spin_unlock_irqrestore(&bar->lock, flags);
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}
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void
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g84_bar_flush(struct nvkm_bar *obj)
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{
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struct nv50_bar *bar = container_of(obj, typeof(*bar), base);
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struct nvkm_device *device = bar->base.subdev.device;
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unsigned long flags;
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spin_lock_irqsave(&bar->lock, flags);
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nvkm_wr32(device, 0x070000, 0x00000001);
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nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, 0x070000) & 0x00000002))
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break;
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);
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spin_unlock_irqrestore(&bar->lock, flags);
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}
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static int
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nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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static struct lock_class_key bar1_lock;
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static struct lock_class_key bar3_lock;
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struct nvkm_device *device = nv_device(parent);
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struct nvkm_vm *vm;
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struct nv50_bar *bar;
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u64 start, limit;
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int ret;
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ret = nvkm_bar_create(parent, engine, oclass, &bar);
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*pobject = nv_object(bar);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(device, 0x20000, 0, false, NULL, &bar->mem);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(device, (device->chipset == 0x50) ?
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0x1400 : 0x200, 0, false, bar->mem,
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&bar->pad);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(device, 0x4000, 0, false, bar->mem, &bar->pgd);
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if (ret)
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return ret;
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/* BAR3 */
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start = 0x0100000000ULL;
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limit = start + nv_device_resource_len(device, 3);
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ret = nvkm_vm_new(device, start, limit, start, &bar3_lock, &vm);
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if (ret)
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return ret;
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atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
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ret = nvkm_vm_boot(vm, limit-- - start);
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if (ret)
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return ret;
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ret = nvkm_vm_ref(vm, &bar->bar3_vm, bar->pgd);
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nvkm_vm_ref(NULL, &vm, NULL);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar3);
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if (ret)
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return ret;
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nvkm_kmap(bar->bar3);
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nvkm_wo32(bar->bar3, 0x00, 0x7fc00000);
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nvkm_wo32(bar->bar3, 0x04, lower_32_bits(limit));
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nvkm_wo32(bar->bar3, 0x08, lower_32_bits(start));
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nvkm_wo32(bar->bar3, 0x0c, upper_32_bits(limit) << 24 |
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upper_32_bits(start));
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nvkm_wo32(bar->bar3, 0x10, 0x00000000);
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nvkm_wo32(bar->bar3, 0x14, 0x00000000);
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nvkm_done(bar->bar3);
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/* BAR1 */
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start = 0x0000000000ULL;
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limit = start + nv_device_resource_len(device, 1);
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ret = nvkm_vm_new(device, start, limit--, start, &bar1_lock, &vm);
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if (ret)
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return ret;
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atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
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ret = nvkm_vm_ref(vm, &bar->bar1_vm, bar->pgd);
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nvkm_vm_ref(NULL, &vm, NULL);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar1);
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if (ret)
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return ret;
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nvkm_kmap(bar->bar1);
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nvkm_wo32(bar->bar1, 0x00, 0x7fc00000);
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nvkm_wo32(bar->bar1, 0x04, lower_32_bits(limit));
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nvkm_wo32(bar->bar1, 0x08, lower_32_bits(start));
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nvkm_wo32(bar->bar1, 0x0c, upper_32_bits(limit) << 24 |
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upper_32_bits(start));
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nvkm_wo32(bar->bar1, 0x10, 0x00000000);
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nvkm_wo32(bar->bar1, 0x14, 0x00000000);
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nvkm_done(bar->bar1);
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bar->base.kmap = nv50_bar_kmap;
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bar->base.umap = nv50_bar_umap;
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bar->base.unmap = nv50_bar_unmap;
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if (device->chipset == 0x50)
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bar->base.flush = nv50_bar_flush;
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else
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bar->base.flush = g84_bar_flush;
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spin_lock_init(&bar->lock);
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return 0;
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}
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static void
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nv50_bar_dtor(struct nvkm_object *object)
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{
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struct nv50_bar *bar = (void *)object;
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nvkm_gpuobj_del(&bar->bar1);
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nvkm_vm_ref(NULL, &bar->bar1_vm, bar->pgd);
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nvkm_gpuobj_del(&bar->bar3);
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if (bar->bar3_vm) {
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nvkm_memory_del(&bar->bar3_vm->pgt[0].mem[0]);
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nvkm_vm_ref(NULL, &bar->bar3_vm, bar->pgd);
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}
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nvkm_gpuobj_del(&bar->pgd);
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nvkm_gpuobj_del(&bar->pad);
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nvkm_gpuobj_del(&bar->mem);
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nvkm_bar_destroy(&bar->base);
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}
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static int
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nv50_bar_init(struct nvkm_object *object)
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{
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struct nv50_bar *bar = (void *)object;
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struct nvkm_device *device = bar->base.subdev.device;
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int ret, i;
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ret = nvkm_bar_init(&bar->base);
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if (ret)
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return ret;
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nvkm_mask(device, 0x000200, 0x00000100, 0x00000000);
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nvkm_mask(device, 0x000200, 0x00000100, 0x00000100);
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nvkm_wr32(device, 0x100c80, 0x00060001);
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if (nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, 0x100c80) & 0x00000001))
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break;
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) < 0)
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return -EBUSY;
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nvkm_wr32(device, 0x001704, 0x00000000 | bar->mem->addr >> 12);
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nvkm_wr32(device, 0x001704, 0x40000000 | bar->mem->addr >> 12);
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nvkm_wr32(device, 0x001708, 0x80000000 | bar->bar1->node->offset >> 4);
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nvkm_wr32(device, 0x00170c, 0x80000000 | bar->bar3->node->offset >> 4);
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for (i = 0; i < 8; i++)
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nvkm_wr32(device, 0x001900 + (i * 4), 0x00000000);
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return 0;
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}
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static int
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nv50_bar_fini(struct nvkm_object *object, bool suspend)
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{
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struct nv50_bar *bar = (void *)object;
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return nvkm_bar_fini(&bar->base, suspend);
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}
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struct nvkm_oclass
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nv50_bar_oclass = {
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.handle = NV_SUBDEV(BAR, 0x50),
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.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = nv50_bar_ctor,
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.dtor = nv50_bar_dtor,
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.init = nv50_bar_init,
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.fini = nv50_bar_fini,
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},
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};
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