Atish Patra efca139892 RISC-V: Introduce a new config for SBI v0.1 ... We now have SBI v0.2 which is more scalable and extendable to handle future needs for RISC-V supervisor interfaces. Introduce a new config and move all SBI v0.1 code under that config. This allows to implement the new replacement SBI extensions cleanly and remove v0.1 extensions easily in future. Currently, the config is enabled by default. Once all M-mode software, with v0.1, is no longer in use, this config option and all relevant code can be easily removed. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2020-03-31 11:25:40 -07:00
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vdso	riscv: delete temporary files	2020-01-18 13:22:13 -08:00
.gitignore	RISC-V: Build Infrastructure	2017-09-26 15:26:49 -07:00
asm-offsets.c	riscv: abstract out CSR names for supervisor vs machine mode	2019-11-05 09:20:42 -08:00
cacheinfo.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	2019-06-05 17:36:37 +02:00
clint.c	riscv: provide native clint access for M-mode	2019-11-17 15:17:39 -08:00
cpu.c	RISC-V: Remove unsupported isa string info print	2019-10-28 11:13:59 -07:00
cpufeature.c	riscv: add missing header file includes	2019-10-28 00:46:01 -07:00
entry.S	RISC-V: Inline the assembly register save/restore macros	2020-03-03 10:33:21 -08:00
fpu.S	riscv: abstract out CSR names for supervisor vs machine mode	2019-11-05 09:20:42 -08:00
ftrace.c	riscv: patch code by fixmap mapping	2020-03-26 09:24:55 -07:00
head.h	riscv: add prototypes for assembly language functions from head.S	2019-10-28 00:46:00 -07:00
head.S	riscv: set pmp configuration if kernel is running in M-mode	2020-02-18 09:41:24 -08:00
irq.c	riscv: prefix IRQ_ macro names with an RV_ namespace	2020-01-04 21:48:59 -08:00
Makefile	riscv: introduce interfaces to patch kernel code	2020-03-26 09:24:52 -07:00
mcount-dyn.S	riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support	2018-04-02 19:59:13 -07:00
mcount.S	RISC-V: remove the unused return_to_handler export	2018-10-22 17:38:12 -07:00
module-sections.c	riscv: add missing header file includes	2019-10-28 00:46:01 -07:00
module.c	riscv: Use pr_warn instead of pr_warning	2019-10-18 10:48:36 +02:00
module.lds	RISC-V: Add section of GOT.PLT for kernel module	2018-04-02 20:00:54 -07:00
patch.c	riscv: introduce interfaces to patch kernel code	2020-03-26 09:24:52 -07:00
perf_callchain.c	riscv: abstract out CSR names for supervisor vs machine mode	2019-11-05 09:20:42 -08:00
perf_event.c	RISC-V: Access CSRs using CSR numbers	2019-05-16 20:42:11 -07:00
perf_regs.c	riscv: Add support for perf registers sampling	2019-09-05 00:48:58 -07:00
process.c	RISC-V: Stop relying on GCC's register allocator's hueristics	2020-03-03 10:28:13 -08:00
ptrace.c	seccomp updates for v5.5	2019-11-30 17:23:16 -08:00
reset.c	riscv: cleanup the default power off implementation	2019-11-13 13:22:52 -08:00
riscv_ksyms.c	riscv: Add KASAN support	2020-01-22 13:09:58 -08:00
sbi.c	RISC-V: Introduce a new config for SBI v0.1	2020-03-31 11:25:40 -07:00
setup.c	RISC-V: Add basic support for SBI v0.2	2020-03-31 11:25:29 -07:00
signal.c	riscv: add nommu support	2019-11-17 15:17:39 -08:00
smp.c	riscv: provide native clint access for M-mode	2019-11-17 15:17:39 -08:00
smpboot.c	riscv: provide native clint access for M-mode	2019-11-17 15:17:39 -08:00
stacktrace.c	RISC-V: Stop relying on GCC's register allocator's hueristics	2020-03-03 10:28:13 -08:00
sys_riscv.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	2019-06-05 17:36:37 +02:00
syscall_table.c	riscv: add missing header file includes	2019-10-28 00:46:01 -07:00
time.c	riscv: add missing header file includes	2019-10-28 00:46:01 -07:00
traps.c	riscv: add macro to get instruction length	2020-03-26 09:24:49 -07:00
vdso.c	riscv: add missing header file includes	2019-10-28 00:46:01 -07:00
vmlinux.lds.S	riscv: add alignment for text, rodata and data sections	2020-03-26 09:24:42 -07:00