forked from Minki/linux
158 lines
3.3 KiB
C
158 lines
3.3 KiB
C
/*
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* linux/arch/xtensa/kernel/irq.c
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*
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* Xtensa built-in interrupt controller and some generic functions copied
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* from i386.
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*
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* Copyright (C) 2002 - 2006 Tensilica, Inc.
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* Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
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*
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*
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* Chris Zankel <chris@zankel.net>
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* Kevin Chea
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*
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*/
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#include <linux/module.h>
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#include <linux/seq_file.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel_stat.h>
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#include <asm/uaccess.h>
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#include <asm/platform.h>
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static unsigned int cached_irq_mask;
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atomic_t irq_err_count;
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/*
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* do_IRQ handles all normal device IRQ's (the special
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* SMP cross-CPU interrupts have their own specific
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* handlers).
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*/
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asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
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{
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struct pt_regs *old_regs = set_irq_regs(regs);
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if (irq >= NR_IRQS) {
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printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
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__func__, irq);
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}
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irq_enter();
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#ifdef CONFIG_DEBUG_STACKOVERFLOW
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/* Debugging check for stack overflow: is there less than 1KB free? */
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{
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unsigned long sp;
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__asm__ __volatile__ ("mov %0, a1\n" : "=a" (sp));
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sp &= THREAD_SIZE - 1;
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if (unlikely(sp < (sizeof(thread_info) + 1024)))
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printk("Stack overflow in do_IRQ: %ld\n",
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sp - sizeof(struct thread_info));
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}
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#endif
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generic_handle_irq(irq);
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irq_exit();
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set_irq_regs(old_regs);
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}
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int arch_show_interrupts(struct seq_file *p, int prec)
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{
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int j;
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seq_printf(p, "%*s: ", prec, "NMI");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", nmi_count(j));
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seq_putc(p, '\n');
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seq_printf(p, "%*s: ", prec, "ERR");
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seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
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return 0;
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}
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static void xtensa_irq_mask(struct irq_chip *d)
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{
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cached_irq_mask &= ~(1 << d->irq);
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set_sr (cached_irq_mask, INTENABLE);
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}
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static void xtensa_irq_unmask(struct irq_chip *d)
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{
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cached_irq_mask |= 1 << d->irq;
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set_sr (cached_irq_mask, INTENABLE);
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}
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static void xtensa_irq_enable(struct irq_chip *d)
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{
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variant_irq_enable(d->irq);
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xtensa_irq_unmask(d->irq);
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}
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static void xtensa_irq_disable(struct irq_chip *d)
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{
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xtensa_irq_mask(d->irq);
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variant_irq_disable(d->irq);
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}
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static void xtensa_irq_ack(struct irq_chip *d)
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{
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set_sr(1 << d->irq, INTCLEAR);
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}
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static int xtensa_irq_retrigger(struct irq_chip *d)
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{
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set_sr (1 << d->irq, INTSET);
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return 1;
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}
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static struct irq_chip xtensa_irq_chip = {
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.name = "xtensa",
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.irq_enable = xtensa_irq_enable,
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.irq_disable = xtensa_irq_disable,
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.irq_mask = xtensa_irq_mask,
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.irq_unmask = xtensa_irq_unmask,
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.irq_ack = xtensa_irq_ack,
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.irq_retrigger = xtensa_irq_retrigger,
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};
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void __init init_IRQ(void)
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{
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int index;
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for (index = 0; index < XTENSA_NR_IRQS; index++) {
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int mask = 1 << index;
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if (mask & XCHAL_INTTYPE_MASK_SOFTWARE)
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irq_set_chip_and_handler(index, &xtensa_irq_chip,
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handle_simple_irq);
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else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE)
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irq_set_chip_and_handler(index, &xtensa_irq_chip,
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handle_edge_irq);
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else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL)
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irq_set_chip_and_handler(index, &xtensa_irq_chip,
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handle_level_irq);
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else if (mask & XCHAL_INTTYPE_MASK_TIMER)
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irq_set_chip_and_handler(index, &xtensa_irq_chip,
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handle_edge_irq);
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else /* XCHAL_INTTYPE_MASK_WRITE_ERROR */
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/* XCHAL_INTTYPE_MASK_NMI */
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irq_set_chip_and_handler(index, &xtensa_irq_chip,
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handle_level_irq);
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}
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cached_irq_mask = 0;
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variant_init_irq();
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}
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