Kan Liang ee13938543 perf/x86/intel/uncore: Reduce the number of CBOX counters ... An oops is triggered by the fuzzy test. [ 327.853081] unchecked MSR access error: RDMSR from 0x70c at rIP: 0xffffffffc082c820 (uncore_msr_read_counter+0x10/0x50 [intel_uncore]) [ 327.853083] Call Trace: [ 327.853085] <IRQ> [ 327.853089] uncore_pmu_event_start+0x85/0x170 [intel_uncore] [ 327.853093] uncore_pmu_event_add+0x1a4/0x410 [intel_uncore] [ 327.853097] ? event_sched_in.isra.118+0xca/0x240 There are 2 GP counters for each CBOX, but the current code claims 4 counters. Accessing the invalid registers triggers the oops. Fixes: 6e394376ee ("perf/x86/intel/uncore: Add Intel Icelake uncore support") Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20200925134905.8839-3-kan.liang@linux.intel.com		2020-09-29 09:57:01 +02:00
..
amd	perf/amd/uncore: Inform the user how many counters each uncore PMU has	2020-09-24 15:55:50 +02:00
intel	perf/x86/intel/uncore: Reduce the number of CBOX counters	2020-09-29 09:57:01 +02:00
zhaoxin	x86/perf: Fix a typo	2020-07-22 10:22:08 +02:00
core.c	perf/x86/amd: Fix sampling Large Increment per Cycle events	2020-09-10 11:19:35 +02:00
Kconfig	treewide: replace '---help---' in Kconfig files with 'help'	2020-06-14 01:57:21 +09:00
Makefile	perf/x86/rapl: Fix RAPL config variable bug	2020-06-02 11:52:56 +02:00
msr.c	perf/x86/msr: Add Tremont support	2020-02-11 13:17:50 +01:00
perf_event.h	perf/x86/intel: Support TopDown metrics on Ice Lake	2020-08-18 16:34:37 +02:00
probe.c	perf/x86/rapl: Make perf_probe_msr() more robust and flexible	2020-05-28 07:58:55 +02:00
probe.h	perf/x86: Add MSR probe interface	2019-06-24 19:28:31 +02:00
rapl.c	perf/x86/rapl: Add AMD Fam19h RAPL support	2020-09-10 11:19:36 +02:00