Lars-Peter Clausen
ee0ebe8100
spi: cadence: Fix 3-to-8 mux mode
...
In 3-to-8 mux mode for the CS pins we need to set the PERI_SEL bit in the
control register. Currently the driver never sets this bit even when
configured for 3-to-8 mux mode. This patch adds code which sets the bit
during device initialization when necessary.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de >
Acked-by: Harini Katakam <harinik@xilinx.com >
Signed-off-by: Mark Brown <broonie@kernel.org >
2014-11-28 11:42:11 +00:00
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