forked from Minki/linux
6a33fc8cac
- dove - fix section mismatch (all callers are already _init, so it's just a space issue) -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.20 (GNU/Linux) iQEcBAABAgAGBQJR8WKEAAoJEAi3KVZQDZAee5EH+wfCyJExLJIEl4WvqOAL/Nme w5WGU4NONKb4nP8OTzuN0iR1+IHU6M3kiunn44iW5DzL7Eh6xP/EtW/f43SpjXTN slIeEfgLSsZkLt4lTlDjja/K4cB61LbZ/T/SyeY4VnoIHAUr/Z0hR4OyuDqWRIai wMZ6X54oNz+EKXG2mXxDBysPmxywoZU8dLQfOgjYgunSk2g8D5EU03fhfLZwHRQt cn5EEmNpjalDD4j2X04hyI5iZcH1OguaElYj5YuyYqf+8prTuNNoJ7g2eaW2Fy61 bHgx0N38rY0mhmTgVVSS6y7n0zlSlC2nl0BrjDKBAs9ekYq2NAXO9AohveOuYj0= =kbQG -----END PGP SIGNATURE----- Merge tag 'fixes-non-3.12' of git://git.infradead.org/linux-mvebu into next/fixes-non-critical From Jason Cooper: mvebu fixes-non-critical for v3.12 - dove - fix section mismatch (all callers are already _init, so it's just a space issue) * tag 'fixes-non-3.12' of git://git.infradead.org/linux-mvebu: ARM: dove: fix missing __init section of dove_mpp_gpio_mode + Linux 3.11-rc2 Signed-off-by: Olof Johansson <olof@lixom.net>
52 lines
1.5 KiB
ArmAsm
52 lines
1.5 KiB
ArmAsm
/*
|
|
* Shared SCU setup for mach-shmobile
|
|
*
|
|
* Copyright (C) 2012 Bastian Hecht
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
* MA 02111-1307 USA
|
|
*/
|
|
|
|
#include <linux/linkage.h>
|
|
#include <linux/init.h>
|
|
#include <asm/memory.h>
|
|
|
|
/*
|
|
* Boot code for secondary CPUs.
|
|
*
|
|
* First we turn on L1 cache coherency for our CPU. Then we jump to
|
|
* shmobile_invalidate_start that invalidates the cache and hands over control
|
|
* to the common ARM startup code.
|
|
*/
|
|
ENTRY(shmobile_boot_scu)
|
|
@ r0 = SCU base address
|
|
mrc p15, 0, r1, c0, c0, 5 @ read MIPDR
|
|
and r1, r1, #3 @ mask out cpu ID
|
|
lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits
|
|
ldr r2, [r0, #8] @ SCU Power Status Register
|
|
mov r3, #3
|
|
lsl r3, r3, r1
|
|
bic r2, r2, r3 @ Clear bits of our CPU (Run Mode)
|
|
str r2, [r0, #8] @ write back
|
|
|
|
b shmobile_invalidate_start
|
|
ENDPROC(shmobile_boot_scu)
|
|
|
|
.text
|
|
.align 2
|
|
.globl shmobile_scu_base
|
|
shmobile_scu_base:
|
|
.space 4
|