57007bfb54
The dt-bindings for the UART controller only allow the following values
for Meson8 SoCs:
- "amlogic,meson8-uart", "amlogic,meson-ao-uart"
- "amlogic,meson8-uart"
Use the correct fallback compatible string "amlogic,meson-ao-uart" for
AO UART. Drop the "amlogic,meson-uart" compatible string from the EE
domain UART controllers.
Also update the order of the clocks to match the order defined in the
yaml schema.
Fixes: 6ca7750205 ("ARM: dts: meson8: use stable UART bindings with correct gate clock")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20211227180026.4068352-3-martin.blumenstingl@googlemail.com
787 lines
17 KiB
Plaintext
787 lines
17 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright 2014 Carlo Caione <carlo@caione.org>
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*/
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#include <dt-bindings/clock/meson8-ddr-clkc.h>
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#include <dt-bindings/clock/meson8b-clkc.h>
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#include <dt-bindings/gpio/meson8-gpio.h>
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#include <dt-bindings/power/meson8-power.h>
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#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
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#include <dt-bindings/reset/amlogic,meson8b-reset.h>
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#include <dt-bindings/thermal/thermal.h>
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#include "meson.dtsi"
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/ {
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model = "Amlogic Meson8 SoC";
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compatible = "amlogic,meson8";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x200>;
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enable-method = "amlogic,meson8-smp";
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resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPUCLK>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu1: cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x201>;
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enable-method = "amlogic,meson8-smp";
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resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPUCLK>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu2: cpu@202 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x202>;
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enable-method = "amlogic,meson8-smp";
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resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPUCLK>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu3: cpu@203 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x203>;
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enable-method = "amlogic,meson8-smp";
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resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPUCLK>;
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#cooling-cells = <2>; /* min followed by max */
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};
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};
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cpu_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-96000000 {
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opp-hz = /bits/ 64 <96000000>;
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opp-microvolt = <825000>;
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};
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opp-192000000 {
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opp-hz = /bits/ 64 <192000000>;
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opp-microvolt = <825000>;
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};
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opp-312000000 {
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opp-hz = /bits/ 64 <312000000>;
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opp-microvolt = <825000>;
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};
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <825000>;
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};
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opp-504000000 {
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opp-hz = /bits/ 64 <504000000>;
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opp-microvolt = <825000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <850000>;
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};
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opp-720000000 {
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opp-hz = /bits/ 64 <720000000>;
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opp-microvolt = <850000>;
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};
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opp-816000000 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <875000>;
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};
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opp-1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <925000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <975000>;
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};
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opp-1416000000 {
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opp-hz = /bits/ 64 <1416000000>;
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opp-microvolt = <1025000>;
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};
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opp-1608000000 {
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opp-hz = /bits/ 64 <1608000000>;
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opp-microvolt = <1100000>;
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};
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opp-1800000000 {
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status = "disabled";
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <1125000>;
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};
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opp-1992000000 {
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status = "disabled";
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opp-hz = /bits/ 64 <1992000000>;
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opp-microvolt = <1150000>;
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};
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};
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gpu_opp_table: gpu-opp-table {
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compatible = "operating-points-v2";
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opp-182142857 {
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opp-hz = /bits/ 64 <182142857>;
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opp-microvolt = <1150000>;
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};
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opp-318750000 {
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opp-hz = /bits/ 64 <318750000>;
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opp-microvolt = <1150000>;
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};
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opp-425000000 {
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opp-hz = /bits/ 64 <425000000>;
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opp-microvolt = <1150000>;
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};
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opp-510000000 {
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opp-hz = /bits/ 64 <510000000>;
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opp-microvolt = <1150000>;
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};
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opp-637500000 {
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opp-hz = /bits/ 64 <637500000>;
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opp-microvolt = <1150000>;
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turbo-mode;
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};
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* 2 MiB reserved for Hardware ROM Firmware? */
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hwrom@0 {
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reg = <0x0 0x200000>;
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no-map;
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};
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/*
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* 1 MiB reserved for the "ARM Power Firmware": this is ARM
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* code which is responsible for system suspend. It loads a
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* piece of ARC code ("arc_power" in the vendor u-boot tree)
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* into SRAM, executes that and shuts down the (last) ARM core.
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* The arc_power firmware then checks various wakeup sources
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* (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
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* simply the power key) and re-starts the ARM core once it
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* detects a wakeup request.
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*/
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power-firmware@4f00000 {
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reg = <0x4f00000 0x100000>;
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no-map;
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};
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};
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thermal-zones {
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soc {
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polling-delay-passive = <250>; /* milliseconds */
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polling-delay = <1000>; /* milliseconds */
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thermal-sensors = <&thermal_sensor>;
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cooling-maps {
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map0 {
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trip = <&soc_passive>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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map1 {
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trip = <&soc_hot>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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trips {
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soc_passive: soc-passive {
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temperature = <80000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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soc_hot: soc-hot {
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temperature = <90000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "hot";
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};
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soc_critical: soc-critical {
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temperature = <110000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "critical";
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};
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};
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};
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};
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mmcbus: bus@c8000000 {
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compatible = "simple-bus";
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reg = <0xc8000000 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xc8000000 0x8000>;
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ddr_clkc: clock-controller@400 {
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compatible = "amlogic,meson8-ddr-clkc";
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reg = <0x400 0x20>;
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clocks = <&xtal>;
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clock-names = "xtal";
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#clock-cells = <1>;
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};
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dmcbus: bus@6000 {
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compatible = "simple-bus";
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reg = <0x6000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x6000 0x400>;
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canvas: video-lut@20 {
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compatible = "amlogic,meson8-canvas",
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"amlogic,canvas";
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reg = <0x20 0x14>;
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};
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};
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};
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apb: bus@d0000000 {
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compatible = "simple-bus";
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reg = <0xd0000000 0x200000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xd0000000 0x200000>;
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mali: gpu@c0000 {
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compatible = "amlogic,meson8-mali", "arm,mali-450";
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reg = <0xc0000 0x40000>;
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gp", "gpmmu", "pp", "pmu",
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"pp0", "ppmmu0", "pp1", "ppmmu1",
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"pp2", "ppmmu2", "pp4", "ppmmu4",
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"pp5", "ppmmu5", "pp6", "ppmmu6";
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resets = <&reset RESET_MALI>;
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clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
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clock-names = "bus", "core";
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assigned-clocks = <&clkc CLKID_MALI>;
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assigned-clock-rates = <318750000>;
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operating-points-v2 = <&gpu_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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};
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};
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}; /* end of / */
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&aiu {
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compatible = "amlogic,aiu-meson8", "amlogic,aiu";
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clocks = <&clkc CLKID_AIU_GLUE>,
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<&clkc CLKID_I2S_OUT>,
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<&clkc CLKID_AOCLK_GATE>,
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<&clkc CLKID_CTS_AMCLK>,
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<&clkc CLKID_MIXER_IFACE>,
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<&clkc CLKID_IEC958>,
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<&clkc CLKID_IEC958_GATE>,
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<&clkc CLKID_CTS_MCLK_I958>,
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<&clkc CLKID_CTS_I958>;
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clock-names = "pclk",
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"i2s_pclk",
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"i2s_aoclk",
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"i2s_mclk",
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"i2s_mixer",
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"spdif_pclk",
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"spdif_aoclk",
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"spdif_mclk",
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"spdif_mclk_sel";
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resets = <&reset RESET_AIU>;
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};
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&aobus {
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pmu: pmu@e0 {
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compatible = "amlogic,meson8-pmu", "syscon";
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reg = <0xe0 0x18>;
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};
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pinctrl_aobus: pinctrl@84 {
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compatible = "amlogic,meson8-aobus-pinctrl";
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reg = <0x84 0xc>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio_ao: ao-bank@14 {
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reg = <0x14 0x4>,
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<0x2c 0x4>,
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<0x24 0x8>;
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reg-names = "mux", "pull", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_aobus 0 0 16>;
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};
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i2s_am_clk_pins: i2s-am-clk-out {
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mux {
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groups = "i2s_am_clk_out_ao";
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function = "i2s_ao";
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bias-disable;
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};
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};
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i2s_out_ao_clk_pins: i2s-ao-clk-out {
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mux {
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groups = "i2s_ao_clk_out_ao";
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function = "i2s_ao";
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bias-disable;
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};
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};
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i2s_out_lr_clk_pins: i2s-lr-clk-out {
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mux {
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groups = "i2s_lr_clk_out_ao";
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function = "i2s_ao";
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bias-disable;
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};
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};
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i2s_out_ch01_ao_pins: i2s-out-ch01 {
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mux {
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groups = "i2s_out_ch01_ao";
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function = "i2s_ao";
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bias-disable;
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};
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};
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uart_ao_a_pins: uart_ao_a {
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mux {
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groups = "uart_tx_ao_a", "uart_rx_ao_a";
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function = "uart_ao";
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bias-disable;
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};
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};
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i2c_ao_pins: i2c_mst_ao {
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mux {
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groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
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function = "i2c_mst_ao";
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bias-disable;
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};
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};
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ir_recv_pins: remote {
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mux {
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groups = "remote_input";
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function = "remote";
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bias-disable;
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};
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};
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pwm_f_ao_pins: pwm-f-ao {
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mux {
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groups = "pwm_f_ao";
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function = "pwm_f_ao";
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bias-disable;
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};
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};
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};
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};
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&ao_arc_rproc {
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compatible= "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc";
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amlogic,secbus2 = <&secbus2>;
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sram = <&ao_arc_sram>;
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resets = <&reset RESET_MEDIA_CPU>;
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clocks = <&clkc CLKID_AO_MEDIA_CPU>;
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};
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&cbus {
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reset: reset-controller@4404 {
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compatible = "amlogic,meson8b-reset";
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reg = <0x4404 0x9c>;
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#reset-cells = <1>;
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};
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analog_top: analog-top@81a8 {
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compatible = "amlogic,meson8-analog-top", "syscon";
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reg = <0x81a8 0x14>;
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};
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pwm_ef: pwm@86c0 {
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compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
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reg = <0x86c0 0x10>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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clock-measure@8758 {
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compatible = "amlogic,meson8-clk-measure";
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reg = <0x8758 0x1c>;
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};
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pinctrl_cbus: pinctrl@9880 {
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compatible = "amlogic,meson8-cbus-pinctrl";
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reg = <0x9880 0x10>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio: banks@80b0 {
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reg = <0x80b0 0x28>,
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<0x80e8 0x18>,
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<0x8120 0x18>,
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<0x8030 0x30>;
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reg-names = "mux", "pull", "pull-enable", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_cbus 0 0 120>;
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};
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sd_a_pins: sd-a {
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mux {
|
|
groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
|
|
"sd_d3_a", "sd_clk_a", "sd_cmd_a";
|
|
function = "sd_a";
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
sd_b_pins: sd-b {
|
|
mux {
|
|
groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
|
|
"sd_d3_b", "sd_clk_b", "sd_cmd_b";
|
|
function = "sd_b";
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
sd_c_pins: sd-c {
|
|
mux {
|
|
groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
|
|
"sd_d3_c", "sd_clk_c", "sd_cmd_c";
|
|
function = "sd_c";
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
sdxc_b_pins: sdxc-b {
|
|
mux {
|
|
groups = "sdxc_d0_b", "sdxc_d13_b",
|
|
"sdxc_clk_b", "sdxc_cmd_b";
|
|
function = "sdxc_b";
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
spdif_out_pins: spdif-out {
|
|
mux {
|
|
groups = "spdif_out";
|
|
function = "spdif";
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
spi_nor_pins: nor {
|
|
mux {
|
|
groups = "nor_d", "nor_q", "nor_c", "nor_cs";
|
|
function = "nor";
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
eth_pins: ethernet {
|
|
mux {
|
|
groups = "eth_tx_clk_50m", "eth_tx_en",
|
|
"eth_txd1", "eth_txd0",
|
|
"eth_rx_clk_in", "eth_rx_dv",
|
|
"eth_rxd1", "eth_rxd0", "eth_mdio",
|
|
"eth_mdc";
|
|
function = "ethernet";
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
pwm_e_pins: pwm-e {
|
|
mux {
|
|
groups = "pwm_e";
|
|
function = "pwm_e";
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
uart_a1_pins: uart-a1 {
|
|
mux {
|
|
groups = "uart_tx_a1",
|
|
"uart_rx_a1";
|
|
function = "uart_a";
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
uart_a1_cts_rts_pins: uart-a1-cts-rts {
|
|
mux {
|
|
groups = "uart_cts_a1",
|
|
"uart_rts_a1";
|
|
function = "uart_a";
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&ahb_sram {
|
|
ao_arc_sram: ao-arc-sram@0 {
|
|
compatible = "amlogic,meson8-ao-arc-sram";
|
|
reg = <0x0 0x8000>;
|
|
pool;
|
|
};
|
|
|
|
smp-sram@1ff80 {
|
|
compatible = "amlogic,meson8-smp-sram";
|
|
reg = <0x1ff80 0x8>;
|
|
};
|
|
};
|
|
|
|
&efuse {
|
|
compatible = "amlogic,meson8-efuse";
|
|
clocks = <&clkc CLKID_EFUSE>;
|
|
clock-names = "core";
|
|
|
|
temperature_calib: calib@1f4 {
|
|
/* only the upper two bytes are relevant */
|
|
reg = <0x1f4 0x4>;
|
|
};
|
|
};
|
|
|
|
ðmac {
|
|
clocks = <&clkc CLKID_ETH>;
|
|
clock-names = "stmmaceth";
|
|
|
|
power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
|
|
};
|
|
|
|
&gpio_intc {
|
|
compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc";
|
|
status = "okay";
|
|
};
|
|
|
|
&hhi {
|
|
clkc: clock-controller {
|
|
compatible = "amlogic,meson8-clkc";
|
|
clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
|
|
clock-names = "xtal", "ddr_pll";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
pwrc: power-controller {
|
|
compatible = "amlogic,meson8-pwrc";
|
|
#power-domain-cells = <1>;
|
|
amlogic,ao-sysctrl = <&pmu>;
|
|
clocks = <&clkc CLKID_VPU>;
|
|
clock-names = "vpu";
|
|
assigned-clocks = <&clkc CLKID_VPU>;
|
|
assigned-clock-rates = <364285714>;
|
|
};
|
|
};
|
|
|
|
&hwrng {
|
|
compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
|
|
clocks = <&clkc CLKID_RNG0>;
|
|
clock-names = "core";
|
|
};
|
|
|
|
&i2c_AO {
|
|
clocks = <&clkc CLKID_CLK81>;
|
|
};
|
|
|
|
&i2c_A {
|
|
clocks = <&clkc CLKID_CLK81>;
|
|
};
|
|
|
|
&i2c_B {
|
|
clocks = <&clkc CLKID_CLK81>;
|
|
};
|
|
|
|
&L2 {
|
|
arm,data-latency = <3 3 3>;
|
|
arm,tag-latency = <2 2 2>;
|
|
arm,filter-ranges = <0x100000 0xc0000000>;
|
|
prefetch-data = <1>;
|
|
prefetch-instr = <1>;
|
|
arm,shared-override;
|
|
};
|
|
|
|
&periph {
|
|
scu@0 {
|
|
compatible = "arm,cortex-a9-scu";
|
|
reg = <0x0 0x100>;
|
|
};
|
|
|
|
timer@200 {
|
|
compatible = "arm,cortex-a9-global-timer";
|
|
reg = <0x200 0x20>;
|
|
interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
|
|
clocks = <&clkc CLKID_PERIPH>;
|
|
|
|
/*
|
|
* the arm_global_timer driver currently does not handle clock
|
|
* rate changes. Keep it disabled for now.
|
|
*/
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@600 {
|
|
compatible = "arm,cortex-a9-twd-timer";
|
|
reg = <0x600 0x20>;
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
|
|
clocks = <&clkc CLKID_PERIPH>;
|
|
};
|
|
};
|
|
|
|
&pwm_ab {
|
|
compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
|
|
};
|
|
|
|
&pwm_cd {
|
|
compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
|
|
};
|
|
|
|
&rtc {
|
|
compatible = "amlogic,meson8-rtc";
|
|
resets = <&reset RESET_RTC>;
|
|
};
|
|
|
|
&saradc {
|
|
compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
|
|
clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
|
|
clock-names = "clkin", "core";
|
|
amlogic,hhi-sysctrl = <&hhi>;
|
|
nvmem-cells = <&temperature_calib>;
|
|
nvmem-cell-names = "temperature_calib";
|
|
};
|
|
|
|
&sdhc {
|
|
compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
|
|
clocks = <&xtal>,
|
|
<&clkc CLKID_FCLK_DIV4>,
|
|
<&clkc CLKID_FCLK_DIV3>,
|
|
<&clkc CLKID_FCLK_DIV5>,
|
|
<&clkc CLKID_SDHC>;
|
|
clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
|
|
};
|
|
|
|
&secbus {
|
|
secbus2: system-controller@4000 {
|
|
compatible = "amlogic,meson8-secbus2", "syscon";
|
|
reg = <0x4000 0x2000>;
|
|
};
|
|
};
|
|
|
|
&sdio {
|
|
compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
|
|
clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
|
|
clock-names = "core", "clkin";
|
|
};
|
|
|
|
&spifc {
|
|
clocks = <&clkc CLKID_CLK81>;
|
|
};
|
|
|
|
&timer_abcde {
|
|
clocks = <&xtal>, <&clkc CLKID_CLK81>;
|
|
clock-names = "xtal", "pclk";
|
|
};
|
|
|
|
&uart_AO {
|
|
compatible = "amlogic,meson8-uart", "amlogic,meson-ao-uart";
|
|
clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
|
|
clock-names = "xtal", "pclk", "baud";
|
|
};
|
|
|
|
&uart_A {
|
|
compatible = "amlogic,meson8-uart";
|
|
clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
|
|
clock-names = "xtal", "pclk", "baud";
|
|
};
|
|
|
|
&uart_B {
|
|
compatible = "amlogic,meson8-uart";
|
|
clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
|
|
clock-names = "xtal", "pclk", "baud";
|
|
};
|
|
|
|
&uart_C {
|
|
compatible = "amlogic,meson8-uart";
|
|
clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
|
|
clock-names = "xtal", "pclk", "baud";
|
|
};
|
|
|
|
&usb0 {
|
|
compatible = "amlogic,meson8-usb", "snps,dwc2";
|
|
clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
|
|
clock-names = "otg";
|
|
};
|
|
|
|
&usb1 {
|
|
compatible = "amlogic,meson8-usb", "snps,dwc2";
|
|
clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
|
|
clock-names = "otg";
|
|
};
|
|
|
|
&usb0_phy {
|
|
compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
|
|
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
|
|
clock-names = "usb_general", "usb";
|
|
resets = <&reset RESET_USB_OTG>;
|
|
};
|
|
|
|
&usb1_phy {
|
|
compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
|
|
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
|
|
clock-names = "usb_general", "usb";
|
|
resets = <&reset RESET_USB_OTG>;
|
|
};
|