forked from Minki/linux
ecf4b19615
The core irq_set_type() function updates the flow type when the chip callback returns 0. So setting the type is bogus. The new core code allows to update the type in irq_data and return IRQ_SET_MASK_OK_NOCOPY, so the core code will not touch it, except for setting the IRQ_LEVEL flag. Use the proper accessors for setting the irq handlers. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
993 lines
21 KiB
C
993 lines
21 KiB
C
/*
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* arch/powerpc/sysdev/ipic.c
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*
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* IPIC routines implementations.
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*
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* Copyright 2005 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/slab.h>
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#include <linux/stddef.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/sysdev.h>
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#include <linux/device.h>
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#include <linux/bootmem.h>
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#include <linux/spinlock.h>
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#include <linux/fsl_devices.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/ipic.h>
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#include "ipic.h"
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static struct ipic * primary_ipic;
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static struct irq_chip ipic_level_irq_chip, ipic_edge_irq_chip;
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static DEFINE_RAW_SPINLOCK(ipic_lock);
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static struct ipic_info ipic_info[] = {
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[1] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_C,
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.force = IPIC_SIFCR_H,
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.bit = 16,
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.prio_mask = 0,
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},
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[2] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_C,
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.force = IPIC_SIFCR_H,
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.bit = 17,
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.prio_mask = 1,
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},
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[3] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_C,
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.force = IPIC_SIFCR_H,
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.bit = 18,
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.prio_mask = 2,
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},
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[4] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_C,
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.force = IPIC_SIFCR_H,
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.bit = 19,
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.prio_mask = 3,
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},
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[5] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_C,
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.force = IPIC_SIFCR_H,
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.bit = 20,
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.prio_mask = 4,
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},
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[6] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_C,
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.force = IPIC_SIFCR_H,
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.bit = 21,
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.prio_mask = 5,
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},
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[7] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_C,
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.force = IPIC_SIFCR_H,
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.bit = 22,
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.prio_mask = 6,
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},
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[8] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_C,
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.force = IPIC_SIFCR_H,
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.bit = 23,
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.prio_mask = 7,
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},
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[9] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_D,
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.force = IPIC_SIFCR_H,
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.bit = 24,
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.prio_mask = 0,
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},
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[10] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_D,
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.force = IPIC_SIFCR_H,
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.bit = 25,
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.prio_mask = 1,
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},
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[11] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_D,
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.force = IPIC_SIFCR_H,
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.bit = 26,
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.prio_mask = 2,
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},
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[12] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_D,
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.force = IPIC_SIFCR_H,
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.bit = 27,
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.prio_mask = 3,
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},
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[13] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_D,
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.force = IPIC_SIFCR_H,
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.bit = 28,
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.prio_mask = 4,
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},
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[14] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_D,
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.force = IPIC_SIFCR_H,
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.bit = 29,
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.prio_mask = 5,
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},
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[15] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_D,
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.force = IPIC_SIFCR_H,
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.bit = 30,
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.prio_mask = 6,
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},
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[16] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_D,
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.force = IPIC_SIFCR_H,
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.bit = 31,
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.prio_mask = 7,
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},
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[17] = {
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.ack = IPIC_SEPNR,
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.mask = IPIC_SEMSR,
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.prio = IPIC_SMPRR_A,
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.force = IPIC_SEFCR,
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.bit = 1,
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.prio_mask = 5,
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},
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[18] = {
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.ack = IPIC_SEPNR,
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.mask = IPIC_SEMSR,
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.prio = IPIC_SMPRR_A,
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.force = IPIC_SEFCR,
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.bit = 2,
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.prio_mask = 6,
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},
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[19] = {
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.ack = IPIC_SEPNR,
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.mask = IPIC_SEMSR,
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.prio = IPIC_SMPRR_A,
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.force = IPIC_SEFCR,
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.bit = 3,
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.prio_mask = 7,
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},
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[20] = {
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.ack = IPIC_SEPNR,
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.mask = IPIC_SEMSR,
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.prio = IPIC_SMPRR_B,
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.force = IPIC_SEFCR,
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.bit = 4,
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.prio_mask = 4,
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},
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[21] = {
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.ack = IPIC_SEPNR,
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.mask = IPIC_SEMSR,
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.prio = IPIC_SMPRR_B,
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.force = IPIC_SEFCR,
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.bit = 5,
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.prio_mask = 5,
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},
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[22] = {
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.ack = IPIC_SEPNR,
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.mask = IPIC_SEMSR,
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.prio = IPIC_SMPRR_B,
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.force = IPIC_SEFCR,
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.bit = 6,
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.prio_mask = 6,
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},
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[23] = {
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.ack = IPIC_SEPNR,
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.mask = IPIC_SEMSR,
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.prio = IPIC_SMPRR_B,
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.force = IPIC_SEFCR,
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.bit = 7,
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.prio_mask = 7,
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},
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[32] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_A,
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.force = IPIC_SIFCR_H,
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.bit = 0,
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.prio_mask = 0,
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},
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[33] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_A,
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.force = IPIC_SIFCR_H,
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.bit = 1,
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.prio_mask = 1,
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},
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[34] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_A,
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.force = IPIC_SIFCR_H,
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.bit = 2,
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.prio_mask = 2,
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},
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[35] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_A,
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.force = IPIC_SIFCR_H,
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.bit = 3,
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.prio_mask = 3,
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},
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[36] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_A,
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.force = IPIC_SIFCR_H,
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.bit = 4,
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.prio_mask = 4,
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},
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[37] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_A,
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.force = IPIC_SIFCR_H,
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.bit = 5,
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.prio_mask = 5,
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},
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[38] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_A,
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.force = IPIC_SIFCR_H,
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.bit = 6,
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.prio_mask = 6,
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},
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[39] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_A,
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.force = IPIC_SIFCR_H,
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.bit = 7,
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.prio_mask = 7,
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},
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[40] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_B,
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.force = IPIC_SIFCR_H,
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.bit = 8,
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.prio_mask = 0,
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},
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[41] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_B,
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.force = IPIC_SIFCR_H,
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.bit = 9,
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.prio_mask = 1,
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},
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[42] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_B,
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.force = IPIC_SIFCR_H,
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.bit = 10,
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.prio_mask = 2,
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},
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[43] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_B,
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.force = IPIC_SIFCR_H,
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.bit = 11,
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.prio_mask = 3,
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},
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[44] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_B,
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.force = IPIC_SIFCR_H,
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.bit = 12,
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.prio_mask = 4,
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},
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[45] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_B,
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.force = IPIC_SIFCR_H,
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.bit = 13,
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.prio_mask = 5,
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},
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[46] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_B,
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.force = IPIC_SIFCR_H,
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.bit = 14,
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.prio_mask = 6,
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},
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[47] = {
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_B,
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.force = IPIC_SIFCR_H,
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.bit = 15,
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.prio_mask = 7,
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},
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[48] = {
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.mask = IPIC_SEMSR,
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.prio = IPIC_SMPRR_A,
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.force = IPIC_SEFCR,
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.bit = 0,
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.prio_mask = 4,
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},
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[64] = {
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.mask = IPIC_SIMSR_L,
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.prio = IPIC_SMPRR_A,
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.force = IPIC_SIFCR_L,
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.bit = 0,
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.prio_mask = 0,
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},
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[65] = {
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.mask = IPIC_SIMSR_L,
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.prio = IPIC_SMPRR_A,
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.force = IPIC_SIFCR_L,
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.bit = 1,
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.prio_mask = 1,
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},
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[66] = {
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.mask = IPIC_SIMSR_L,
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.prio = IPIC_SMPRR_A,
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.force = IPIC_SIFCR_L,
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.bit = 2,
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.prio_mask = 2,
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},
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[67] = {
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.mask = IPIC_SIMSR_L,
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.prio = IPIC_SMPRR_A,
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.force = IPIC_SIFCR_L,
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.bit = 3,
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.prio_mask = 3,
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},
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[68] = {
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.mask = IPIC_SIMSR_L,
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.prio = IPIC_SMPRR_B,
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.force = IPIC_SIFCR_L,
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.bit = 4,
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.prio_mask = 0,
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},
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[69] = {
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.mask = IPIC_SIMSR_L,
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.prio = IPIC_SMPRR_B,
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.force = IPIC_SIFCR_L,
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.bit = 5,
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.prio_mask = 1,
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},
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[70] = {
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.mask = IPIC_SIMSR_L,
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.prio = IPIC_SMPRR_B,
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.force = IPIC_SIFCR_L,
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.bit = 6,
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.prio_mask = 2,
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},
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[71] = {
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.mask = IPIC_SIMSR_L,
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.prio = IPIC_SMPRR_B,
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.force = IPIC_SIFCR_L,
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.bit = 7,
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.prio_mask = 3,
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},
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[72] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 8,
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},
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[73] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 9,
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},
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[74] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 10,
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},
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[75] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 11,
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},
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[76] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 12,
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},
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[77] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 13,
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},
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[78] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 14,
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},
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[79] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 15,
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},
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[80] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 16,
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},
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[81] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 17,
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},
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[82] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 18,
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},
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[83] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 19,
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},
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[84] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 20,
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},
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[85] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 21,
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},
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[86] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 22,
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},
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[87] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 23,
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},
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[88] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 24,
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},
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[89] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 25,
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},
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[90] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 26,
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},
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[91] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 27,
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},
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[94] = {
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 30,
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},
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};
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static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
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{
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return in_be32(base + (reg >> 2));
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}
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static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)
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{
|
|
out_be32(base + (reg >> 2), value);
|
|
}
|
|
|
|
static inline struct ipic * ipic_from_irq(unsigned int virq)
|
|
{
|
|
return primary_ipic;
|
|
}
|
|
|
|
#define ipic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
|
|
|
|
static void ipic_unmask_irq(struct irq_data *d)
|
|
{
|
|
struct ipic *ipic = ipic_from_irq(d->irq);
|
|
unsigned int src = ipic_irq_to_hw(d->irq);
|
|
unsigned long flags;
|
|
u32 temp;
|
|
|
|
raw_spin_lock_irqsave(&ipic_lock, flags);
|
|
|
|
temp = ipic_read(ipic->regs, ipic_info[src].mask);
|
|
temp |= (1 << (31 - ipic_info[src].bit));
|
|
ipic_write(ipic->regs, ipic_info[src].mask, temp);
|
|
|
|
raw_spin_unlock_irqrestore(&ipic_lock, flags);
|
|
}
|
|
|
|
static void ipic_mask_irq(struct irq_data *d)
|
|
{
|
|
struct ipic *ipic = ipic_from_irq(d->irq);
|
|
unsigned int src = ipic_irq_to_hw(d->irq);
|
|
unsigned long flags;
|
|
u32 temp;
|
|
|
|
raw_spin_lock_irqsave(&ipic_lock, flags);
|
|
|
|
temp = ipic_read(ipic->regs, ipic_info[src].mask);
|
|
temp &= ~(1 << (31 - ipic_info[src].bit));
|
|
ipic_write(ipic->regs, ipic_info[src].mask, temp);
|
|
|
|
/* mb() can't guarantee that masking is finished. But it does finish
|
|
* for nearly all cases. */
|
|
mb();
|
|
|
|
raw_spin_unlock_irqrestore(&ipic_lock, flags);
|
|
}
|
|
|
|
static void ipic_ack_irq(struct irq_data *d)
|
|
{
|
|
struct ipic *ipic = ipic_from_irq(d->irq);
|
|
unsigned int src = ipic_irq_to_hw(d->irq);
|
|
unsigned long flags;
|
|
u32 temp;
|
|
|
|
raw_spin_lock_irqsave(&ipic_lock, flags);
|
|
|
|
temp = 1 << (31 - ipic_info[src].bit);
|
|
ipic_write(ipic->regs, ipic_info[src].ack, temp);
|
|
|
|
/* mb() can't guarantee that ack is finished. But it does finish
|
|
* for nearly all cases. */
|
|
mb();
|
|
|
|
raw_spin_unlock_irqrestore(&ipic_lock, flags);
|
|
}
|
|
|
|
static void ipic_mask_irq_and_ack(struct irq_data *d)
|
|
{
|
|
struct ipic *ipic = ipic_from_irq(d->irq);
|
|
unsigned int src = ipic_irq_to_hw(d->irq);
|
|
unsigned long flags;
|
|
u32 temp;
|
|
|
|
raw_spin_lock_irqsave(&ipic_lock, flags);
|
|
|
|
temp = ipic_read(ipic->regs, ipic_info[src].mask);
|
|
temp &= ~(1 << (31 - ipic_info[src].bit));
|
|
ipic_write(ipic->regs, ipic_info[src].mask, temp);
|
|
|
|
temp = 1 << (31 - ipic_info[src].bit);
|
|
ipic_write(ipic->regs, ipic_info[src].ack, temp);
|
|
|
|
/* mb() can't guarantee that ack is finished. But it does finish
|
|
* for nearly all cases. */
|
|
mb();
|
|
|
|
raw_spin_unlock_irqrestore(&ipic_lock, flags);
|
|
}
|
|
|
|
static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type)
|
|
{
|
|
struct ipic *ipic = ipic_from_irq(d->irq);
|
|
unsigned int src = ipic_irq_to_hw(d->irq);
|
|
unsigned int vold, vnew, edibit;
|
|
|
|
if (flow_type == IRQ_TYPE_NONE)
|
|
flow_type = IRQ_TYPE_LEVEL_LOW;
|
|
|
|
/* ipic supports only low assertion and high-to-low change senses
|
|
*/
|
|
if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) {
|
|
printk(KERN_ERR "ipic: sense type 0x%x not supported\n",
|
|
flow_type);
|
|
return -EINVAL;
|
|
}
|
|
/* ipic supports only edge mode on external interrupts */
|
|
if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !ipic_info[src].ack) {
|
|
printk(KERN_ERR "ipic: edge sense not supported on internal "
|
|
"interrupts\n");
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
irqd_set_trigger_type(d, flow_type);
|
|
if (flow_type & IRQ_TYPE_LEVEL_LOW) {
|
|
__irq_set_handler_locked(d->irq, handle_level_irq);
|
|
d->chip = &ipic_level_irq_chip;
|
|
} else {
|
|
__irq_set_handler_locked(d->irq, handle_edge_irq);
|
|
d->chip = &ipic_edge_irq_chip;
|
|
}
|
|
|
|
/* only EXT IRQ senses are programmable on ipic
|
|
* internal IRQ senses are LEVEL_LOW
|
|
*/
|
|
if (src == IPIC_IRQ_EXT0)
|
|
edibit = 15;
|
|
else
|
|
if (src >= IPIC_IRQ_EXT1 && src <= IPIC_IRQ_EXT7)
|
|
edibit = (14 - (src - IPIC_IRQ_EXT1));
|
|
else
|
|
return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
|
|
|
|
vold = ipic_read(ipic->regs, IPIC_SECNR);
|
|
if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) {
|
|
vnew = vold | (1 << edibit);
|
|
} else {
|
|
vnew = vold & ~(1 << edibit);
|
|
}
|
|
if (vold != vnew)
|
|
ipic_write(ipic->regs, IPIC_SECNR, vnew);
|
|
return IRQ_SET_MASK_OK_NOCOPY;
|
|
}
|
|
|
|
/* level interrupts and edge interrupts have different ack operations */
|
|
static struct irq_chip ipic_level_irq_chip = {
|
|
.name = "IPIC",
|
|
.irq_unmask = ipic_unmask_irq,
|
|
.irq_mask = ipic_mask_irq,
|
|
.irq_mask_ack = ipic_mask_irq,
|
|
.irq_set_type = ipic_set_irq_type,
|
|
};
|
|
|
|
static struct irq_chip ipic_edge_irq_chip = {
|
|
.name = "IPIC",
|
|
.irq_unmask = ipic_unmask_irq,
|
|
.irq_mask = ipic_mask_irq,
|
|
.irq_mask_ack = ipic_mask_irq_and_ack,
|
|
.irq_ack = ipic_ack_irq,
|
|
.irq_set_type = ipic_set_irq_type,
|
|
};
|
|
|
|
static int ipic_host_match(struct irq_host *h, struct device_node *node)
|
|
{
|
|
/* Exact match, unless ipic node is NULL */
|
|
return h->of_node == NULL || h->of_node == node;
|
|
}
|
|
|
|
static int ipic_host_map(struct irq_host *h, unsigned int virq,
|
|
irq_hw_number_t hw)
|
|
{
|
|
struct ipic *ipic = h->host_data;
|
|
|
|
set_irq_chip_data(virq, ipic);
|
|
set_irq_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq);
|
|
|
|
/* Set default irq type */
|
|
set_irq_type(virq, IRQ_TYPE_NONE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ipic_host_xlate(struct irq_host *h, struct device_node *ct,
|
|
const u32 *intspec, unsigned int intsize,
|
|
irq_hw_number_t *out_hwirq, unsigned int *out_flags)
|
|
|
|
{
|
|
/* interrupt sense values coming from the device tree equal either
|
|
* LEVEL_LOW (low assertion) or EDGE_FALLING (high-to-low change)
|
|
*/
|
|
*out_hwirq = intspec[0];
|
|
if (intsize > 1)
|
|
*out_flags = intspec[1];
|
|
else
|
|
*out_flags = IRQ_TYPE_NONE;
|
|
return 0;
|
|
}
|
|
|
|
static struct irq_host_ops ipic_host_ops = {
|
|
.match = ipic_host_match,
|
|
.map = ipic_host_map,
|
|
.xlate = ipic_host_xlate,
|
|
};
|
|
|
|
struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
|
|
{
|
|
struct ipic *ipic;
|
|
struct resource res;
|
|
u32 temp = 0, ret;
|
|
|
|
ret = of_address_to_resource(node, 0, &res);
|
|
if (ret)
|
|
return NULL;
|
|
|
|
ipic = kzalloc(sizeof(*ipic), GFP_KERNEL);
|
|
if (ipic == NULL)
|
|
return NULL;
|
|
|
|
ipic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
|
|
NR_IPIC_INTS,
|
|
&ipic_host_ops, 0);
|
|
if (ipic->irqhost == NULL) {
|
|
kfree(ipic);
|
|
return NULL;
|
|
}
|
|
|
|
ipic->regs = ioremap(res.start, res.end - res.start + 1);
|
|
|
|
ipic->irqhost->host_data = ipic;
|
|
|
|
/* init hw */
|
|
ipic_write(ipic->regs, IPIC_SICNR, 0x0);
|
|
|
|
/* default priority scheme is grouped. If spread mode is required
|
|
* configure SICFR accordingly */
|
|
if (flags & IPIC_SPREADMODE_GRP_A)
|
|
temp |= SICFR_IPSA;
|
|
if (flags & IPIC_SPREADMODE_GRP_B)
|
|
temp |= SICFR_IPSB;
|
|
if (flags & IPIC_SPREADMODE_GRP_C)
|
|
temp |= SICFR_IPSC;
|
|
if (flags & IPIC_SPREADMODE_GRP_D)
|
|
temp |= SICFR_IPSD;
|
|
if (flags & IPIC_SPREADMODE_MIX_A)
|
|
temp |= SICFR_MPSA;
|
|
if (flags & IPIC_SPREADMODE_MIX_B)
|
|
temp |= SICFR_MPSB;
|
|
|
|
ipic_write(ipic->regs, IPIC_SICFR, temp);
|
|
|
|
/* handle MCP route */
|
|
temp = 0;
|
|
if (flags & IPIC_DISABLE_MCP_OUT)
|
|
temp = SERCR_MCPR;
|
|
ipic_write(ipic->regs, IPIC_SERCR, temp);
|
|
|
|
/* handle routing of IRQ0 to MCP */
|
|
temp = ipic_read(ipic->regs, IPIC_SEMSR);
|
|
|
|
if (flags & IPIC_IRQ0_MCP)
|
|
temp |= SEMSR_SIRQ0;
|
|
else
|
|
temp &= ~SEMSR_SIRQ0;
|
|
|
|
ipic_write(ipic->regs, IPIC_SEMSR, temp);
|
|
|
|
primary_ipic = ipic;
|
|
irq_set_default_host(primary_ipic->irqhost);
|
|
|
|
ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
|
|
ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
|
|
|
|
printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS,
|
|
primary_ipic->regs);
|
|
|
|
return ipic;
|
|
}
|
|
|
|
int ipic_set_priority(unsigned int virq, unsigned int priority)
|
|
{
|
|
struct ipic *ipic = ipic_from_irq(virq);
|
|
unsigned int src = ipic_irq_to_hw(virq);
|
|
u32 temp;
|
|
|
|
if (priority > 7)
|
|
return -EINVAL;
|
|
if (src > 127)
|
|
return -EINVAL;
|
|
if (ipic_info[src].prio == 0)
|
|
return -EINVAL;
|
|
|
|
temp = ipic_read(ipic->regs, ipic_info[src].prio);
|
|
|
|
if (priority < 4) {
|
|
temp &= ~(0x7 << (20 + (3 - priority) * 3));
|
|
temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3);
|
|
} else {
|
|
temp &= ~(0x7 << (4 + (7 - priority) * 3));
|
|
temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3);
|
|
}
|
|
|
|
ipic_write(ipic->regs, ipic_info[src].prio, temp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void ipic_set_highest_priority(unsigned int virq)
|
|
{
|
|
struct ipic *ipic = ipic_from_irq(virq);
|
|
unsigned int src = ipic_irq_to_hw(virq);
|
|
u32 temp;
|
|
|
|
temp = ipic_read(ipic->regs, IPIC_SICFR);
|
|
|
|
/* clear and set HPI */
|
|
temp &= 0x7f000000;
|
|
temp |= (src & 0x7f) << 24;
|
|
|
|
ipic_write(ipic->regs, IPIC_SICFR, temp);
|
|
}
|
|
|
|
void ipic_set_default_priority(void)
|
|
{
|
|
ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT);
|
|
ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT);
|
|
ipic_write(primary_ipic->regs, IPIC_SIPRR_C, IPIC_PRIORITY_DEFAULT);
|
|
ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_PRIORITY_DEFAULT);
|
|
ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_PRIORITY_DEFAULT);
|
|
ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_PRIORITY_DEFAULT);
|
|
}
|
|
|
|
void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
|
|
{
|
|
struct ipic *ipic = primary_ipic;
|
|
u32 temp;
|
|
|
|
temp = ipic_read(ipic->regs, IPIC_SERMR);
|
|
temp |= (1 << (31 - mcp_irq));
|
|
ipic_write(ipic->regs, IPIC_SERMR, temp);
|
|
}
|
|
|
|
void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq)
|
|
{
|
|
struct ipic *ipic = primary_ipic;
|
|
u32 temp;
|
|
|
|
temp = ipic_read(ipic->regs, IPIC_SERMR);
|
|
temp &= (1 << (31 - mcp_irq));
|
|
ipic_write(ipic->regs, IPIC_SERMR, temp);
|
|
}
|
|
|
|
u32 ipic_get_mcp_status(void)
|
|
{
|
|
return ipic_read(primary_ipic->regs, IPIC_SERMR);
|
|
}
|
|
|
|
void ipic_clear_mcp_status(u32 mask)
|
|
{
|
|
ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
|
|
}
|
|
|
|
/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
|
|
unsigned int ipic_get_irq(void)
|
|
{
|
|
int irq;
|
|
|
|
BUG_ON(primary_ipic == NULL);
|
|
|
|
#define IPIC_SIVCR_VECTOR_MASK 0x7f
|
|
irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;
|
|
|
|
if (irq == 0) /* 0 --> no irq is pending */
|
|
return NO_IRQ;
|
|
|
|
return irq_linear_revmap(primary_ipic->irqhost, irq);
|
|
}
|
|
|
|
#ifdef CONFIG_SUSPEND
|
|
static struct {
|
|
u32 sicfr;
|
|
u32 siprr[2];
|
|
u32 simsr[2];
|
|
u32 sicnr;
|
|
u32 smprr[2];
|
|
u32 semsr;
|
|
u32 secnr;
|
|
u32 sermr;
|
|
u32 sercr;
|
|
} ipic_saved_state;
|
|
|
|
static int ipic_suspend(struct sys_device *sdev, pm_message_t state)
|
|
{
|
|
struct ipic *ipic = primary_ipic;
|
|
|
|
ipic_saved_state.sicfr = ipic_read(ipic->regs, IPIC_SICFR);
|
|
ipic_saved_state.siprr[0] = ipic_read(ipic->regs, IPIC_SIPRR_A);
|
|
ipic_saved_state.siprr[1] = ipic_read(ipic->regs, IPIC_SIPRR_D);
|
|
ipic_saved_state.simsr[0] = ipic_read(ipic->regs, IPIC_SIMSR_H);
|
|
ipic_saved_state.simsr[1] = ipic_read(ipic->regs, IPIC_SIMSR_L);
|
|
ipic_saved_state.sicnr = ipic_read(ipic->regs, IPIC_SICNR);
|
|
ipic_saved_state.smprr[0] = ipic_read(ipic->regs, IPIC_SMPRR_A);
|
|
ipic_saved_state.smprr[1] = ipic_read(ipic->regs, IPIC_SMPRR_B);
|
|
ipic_saved_state.semsr = ipic_read(ipic->regs, IPIC_SEMSR);
|
|
ipic_saved_state.secnr = ipic_read(ipic->regs, IPIC_SECNR);
|
|
ipic_saved_state.sermr = ipic_read(ipic->regs, IPIC_SERMR);
|
|
ipic_saved_state.sercr = ipic_read(ipic->regs, IPIC_SERCR);
|
|
|
|
if (fsl_deep_sleep()) {
|
|
/* In deep sleep, make sure there can be no
|
|
* pending interrupts, as this can cause
|
|
* problems on 831x.
|
|
*/
|
|
ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
|
|
ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
|
|
ipic_write(ipic->regs, IPIC_SEMSR, 0);
|
|
ipic_write(ipic->regs, IPIC_SERMR, 0);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ipic_resume(struct sys_device *sdev)
|
|
{
|
|
struct ipic *ipic = primary_ipic;
|
|
|
|
ipic_write(ipic->regs, IPIC_SICFR, ipic_saved_state.sicfr);
|
|
ipic_write(ipic->regs, IPIC_SIPRR_A, ipic_saved_state.siprr[0]);
|
|
ipic_write(ipic->regs, IPIC_SIPRR_D, ipic_saved_state.siprr[1]);
|
|
ipic_write(ipic->regs, IPIC_SIMSR_H, ipic_saved_state.simsr[0]);
|
|
ipic_write(ipic->regs, IPIC_SIMSR_L, ipic_saved_state.simsr[1]);
|
|
ipic_write(ipic->regs, IPIC_SICNR, ipic_saved_state.sicnr);
|
|
ipic_write(ipic->regs, IPIC_SMPRR_A, ipic_saved_state.smprr[0]);
|
|
ipic_write(ipic->regs, IPIC_SMPRR_B, ipic_saved_state.smprr[1]);
|
|
ipic_write(ipic->regs, IPIC_SEMSR, ipic_saved_state.semsr);
|
|
ipic_write(ipic->regs, IPIC_SECNR, ipic_saved_state.secnr);
|
|
ipic_write(ipic->regs, IPIC_SERMR, ipic_saved_state.sermr);
|
|
ipic_write(ipic->regs, IPIC_SERCR, ipic_saved_state.sercr);
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
#define ipic_suspend NULL
|
|
#define ipic_resume NULL
|
|
#endif
|
|
|
|
static struct sysdev_class ipic_sysclass = {
|
|
.name = "ipic",
|
|
.suspend = ipic_suspend,
|
|
.resume = ipic_resume,
|
|
};
|
|
|
|
static struct sys_device device_ipic = {
|
|
.id = 0,
|
|
.cls = &ipic_sysclass,
|
|
};
|
|
|
|
static int __init init_ipic_sysfs(void)
|
|
{
|
|
int rc;
|
|
|
|
if (!primary_ipic || !primary_ipic->regs)
|
|
return -ENODEV;
|
|
printk(KERN_DEBUG "Registering ipic with sysfs...\n");
|
|
|
|
rc = sysdev_class_register(&ipic_sysclass);
|
|
if (rc) {
|
|
printk(KERN_ERR "Failed registering ipic sys class\n");
|
|
return -ENODEV;
|
|
}
|
|
rc = sysdev_register(&device_ipic);
|
|
if (rc) {
|
|
printk(KERN_ERR "Failed registering ipic sys device\n");
|
|
return -ENODEV;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
subsys_initcall(init_ipic_sysfs);
|