forked from Minki/linux
6441ab5f8f
Problems with the previous code:
- HDMI just uses WRPLL1 for everything, so dual head cases might not
work sometimes.
- At encoder->mode_set we just write the PLL register without doing
any kind of check (e.g., check if the PLL is already being used).
- There is no way to fail and return error codes at
encoder->mode_set.
- We write to PORT_CLK_SEL at mode_set and we never disable it.
- Machines hang due to wrong clock enable/disable sequence.
So here we rewrite the code, making it a little more like the
pre-Haswell PLL mode set code:
- Check PLL availability at ironlake_crtc_mode_set.
- Try to use both WRPLLs.
- Check if PLLs are used before actually trying to use them, and
properly fail with error messages.
- Enable/disable PORT_CLK_SEL at the right place.
- Add some WARNs to check for bugs.
The next improvement will be to try to reuse PLLs if the timings
match, but this is content for another patch and it's already
documented with a TODO comment.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
597 lines
20 KiB
C
597 lines
20 KiB
C
/*
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* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
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* Copyright (c) 2007-2008 Intel Corporation
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* Jesse Barnes <jesse.barnes@intel.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef __INTEL_DRV_H__
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#define __INTEL_DRV_H__
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#include <linux/i2c.h>
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#include "i915_drm.h"
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#include "i915_drv.h"
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#include "drm_crtc.h"
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#include "drm_crtc_helper.h"
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#include "drm_fb_helper.h"
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#include "drm_dp_helper.h"
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#define _wait_for(COND, MS, W) ({ \
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unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
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int ret__ = 0; \
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while (!(COND)) { \
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if (time_after(jiffies, timeout__)) { \
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ret__ = -ETIMEDOUT; \
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break; \
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} \
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if (W && drm_can_sleep()) { \
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msleep(W); \
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} else { \
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cpu_relax(); \
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} \
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} \
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ret__; \
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})
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#define wait_for_atomic_us(COND, US) ({ \
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unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \
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int ret__ = 0; \
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while (!(COND)) { \
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if (time_after(jiffies, timeout__)) { \
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ret__ = -ETIMEDOUT; \
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break; \
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} \
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cpu_relax(); \
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} \
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ret__; \
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})
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#define wait_for(COND, MS) _wait_for(COND, MS, 1)
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#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
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#define KHz(x) (1000*x)
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#define MHz(x) KHz(1000*x)
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/*
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* Display related stuff
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*/
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/* store information about an Ixxx DVO */
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/* The i830->i865 use multiple DVOs with multiple i2cs */
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/* the i915, i945 have a single sDVO i2c bus - which is different */
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#define MAX_OUTPUTS 6
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/* maximum connectors per crtcs in the mode set */
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#define INTELFB_CONN_LIMIT 4
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#define INTEL_I2C_BUS_DVO 1
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#define INTEL_I2C_BUS_SDVO 2
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/* these are outputs from the chip - integrated only
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external chips are via DVO or SDVO output */
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#define INTEL_OUTPUT_UNUSED 0
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#define INTEL_OUTPUT_ANALOG 1
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#define INTEL_OUTPUT_DVO 2
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#define INTEL_OUTPUT_SDVO 3
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#define INTEL_OUTPUT_LVDS 4
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#define INTEL_OUTPUT_TVOUT 5
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#define INTEL_OUTPUT_HDMI 6
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#define INTEL_OUTPUT_DISPLAYPORT 7
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#define INTEL_OUTPUT_EDP 8
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#define INTEL_DVO_CHIP_NONE 0
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#define INTEL_DVO_CHIP_LVDS 1
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#define INTEL_DVO_CHIP_TMDS 2
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#define INTEL_DVO_CHIP_TVOUT 4
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/* drm_display_mode->private_flags */
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#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
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#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
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#define INTEL_MODE_DP_FORCE_6BPC (0x10)
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/* This flag must be set by the encoder's mode_fixup if it changes the crtc
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* timings in the mode to prevent the crtc fixup from overwriting them.
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* Currently only lvds needs that. */
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#define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
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static inline void
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intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
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int multiplier)
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{
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mode->clock *= multiplier;
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mode->private_flags |= multiplier;
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}
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static inline int
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intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
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{
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return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
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}
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struct intel_framebuffer {
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struct drm_framebuffer base;
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struct drm_i915_gem_object *obj;
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};
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struct intel_fbdev {
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struct drm_fb_helper helper;
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struct intel_framebuffer ifb;
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struct list_head fbdev_list;
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struct drm_display_mode *our_mode;
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};
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struct intel_encoder {
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struct drm_encoder base;
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/*
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* The new crtc this encoder will be driven from. Only differs from
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* base->crtc while a modeset is in progress.
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*/
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struct intel_crtc *new_crtc;
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int type;
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bool needs_tv_clock;
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/*
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* Intel hw has only one MUX where encoders could be clone, hence a
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* simple flag is enough to compute the possible_clones mask.
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*/
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bool cloneable;
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bool connectors_active;
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void (*hot_plug)(struct intel_encoder *);
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void (*pre_enable)(struct intel_encoder *);
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void (*enable)(struct intel_encoder *);
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void (*disable)(struct intel_encoder *);
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void (*post_disable)(struct intel_encoder *);
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/* Read out the current hw state of this connector, returning true if
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* the encoder is active. If the encoder is enabled it also set the pipe
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* it is connected to in the pipe parameter. */
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bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
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int crtc_mask;
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};
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struct intel_connector {
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struct drm_connector base;
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/*
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* The fixed encoder this connector is connected to.
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*/
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struct intel_encoder *encoder;
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/*
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* The new encoder this connector will be driven. Only differs from
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* encoder while a modeset is in progress.
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*/
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struct intel_encoder *new_encoder;
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/* Reads out the current hw, returning true if the connector is enabled
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* and active (i.e. dpms ON state). */
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bool (*get_hw_state)(struct intel_connector *);
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};
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struct intel_crtc {
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struct drm_crtc base;
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enum pipe pipe;
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enum plane plane;
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u8 lut_r[256], lut_g[256], lut_b[256];
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/*
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* Whether the crtc and the connected output pipeline is active. Implies
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* that crtc->enabled is set, i.e. the current mode configuration has
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* some outputs connected to this crtc.
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*/
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bool active;
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bool primary_disabled; /* is the crtc obscured by a plane? */
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bool lowfreq_avail;
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struct intel_overlay *overlay;
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struct intel_unpin_work *unpin_work;
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int fdi_lanes;
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/* Display surface base address adjustement for pageflips. Note that on
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* gen4+ this only adjusts up to a tile, offsets within a tile are
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* handled in the hw itself (with the TILEOFF register). */
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unsigned long dspaddr_offset;
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struct drm_i915_gem_object *cursor_bo;
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uint32_t cursor_addr;
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int16_t cursor_x, cursor_y;
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int16_t cursor_width, cursor_height;
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bool cursor_visible;
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unsigned int bpp;
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/* We can share PLLs across outputs if the timings match */
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struct intel_pch_pll *pch_pll;
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uint32_t ddi_pll_sel;
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};
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struct intel_plane {
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struct drm_plane base;
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enum pipe pipe;
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struct drm_i915_gem_object *obj;
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int max_downscale;
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u32 lut_r[1024], lut_g[1024], lut_b[1024];
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void (*update_plane)(struct drm_plane *plane,
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struct drm_framebuffer *fb,
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struct drm_i915_gem_object *obj,
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int crtc_x, int crtc_y,
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unsigned int crtc_w, unsigned int crtc_h,
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uint32_t x, uint32_t y,
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uint32_t src_w, uint32_t src_h);
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void (*disable_plane)(struct drm_plane *plane);
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int (*update_colorkey)(struct drm_plane *plane,
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struct drm_intel_sprite_colorkey *key);
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void (*get_colorkey)(struct drm_plane *plane,
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struct drm_intel_sprite_colorkey *key);
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};
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struct intel_watermark_params {
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unsigned long fifo_size;
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unsigned long max_wm;
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unsigned long default_wm;
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unsigned long guard_size;
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unsigned long cacheline_size;
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};
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struct cxsr_latency {
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int is_desktop;
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int is_ddr3;
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unsigned long fsb_freq;
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unsigned long mem_freq;
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unsigned long display_sr;
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unsigned long display_hpll_disable;
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unsigned long cursor_sr;
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unsigned long cursor_hpll_disable;
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};
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#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
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#define to_intel_connector(x) container_of(x, struct intel_connector, base)
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#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
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#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
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#define to_intel_plane(x) container_of(x, struct intel_plane, base)
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#define DIP_HEADER_SIZE 5
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#define DIP_TYPE_AVI 0x82
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#define DIP_VERSION_AVI 0x2
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#define DIP_LEN_AVI 13
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#define DIP_AVI_PR_1 0
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#define DIP_AVI_PR_2 1
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#define DIP_TYPE_SPD 0x83
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#define DIP_VERSION_SPD 0x1
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#define DIP_LEN_SPD 25
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#define DIP_SPD_UNKNOWN 0
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#define DIP_SPD_DSTB 0x1
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#define DIP_SPD_DVDP 0x2
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#define DIP_SPD_DVHS 0x3
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#define DIP_SPD_HDDVR 0x4
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#define DIP_SPD_DVC 0x5
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#define DIP_SPD_DSC 0x6
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#define DIP_SPD_VCD 0x7
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#define DIP_SPD_GAME 0x8
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#define DIP_SPD_PC 0x9
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#define DIP_SPD_BD 0xa
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#define DIP_SPD_SCD 0xb
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struct dip_infoframe {
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uint8_t type; /* HB0 */
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uint8_t ver; /* HB1 */
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uint8_t len; /* HB2 - body len, not including checksum */
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uint8_t ecc; /* Header ECC */
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uint8_t checksum; /* PB0 */
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union {
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struct {
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/* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
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uint8_t Y_A_B_S;
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/* PB2 - C 7:6, M 5:4, R 3:0 */
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uint8_t C_M_R;
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/* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
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uint8_t ITC_EC_Q_SC;
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/* PB4 - VIC 6:0 */
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uint8_t VIC;
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/* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
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uint8_t YQ_CN_PR;
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/* PB6 to PB13 */
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uint16_t top_bar_end;
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uint16_t bottom_bar_start;
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uint16_t left_bar_end;
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uint16_t right_bar_start;
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} __attribute__ ((packed)) avi;
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struct {
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uint8_t vn[8];
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uint8_t pd[16];
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uint8_t sdi;
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} __attribute__ ((packed)) spd;
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uint8_t payload[27];
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} __attribute__ ((packed)) body;
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} __attribute__((packed));
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struct intel_hdmi {
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struct intel_encoder base;
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u32 sdvox_reg;
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int ddc_bus;
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int ddi_port;
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uint32_t color_range;
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bool has_hdmi_sink;
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bool has_audio;
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enum hdmi_force_audio force_audio;
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void (*write_infoframe)(struct drm_encoder *encoder,
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struct dip_infoframe *frame);
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void (*set_infoframes)(struct drm_encoder *encoder,
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struct drm_display_mode *adjusted_mode);
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};
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#define DP_RECEIVER_CAP_SIZE 0xf
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#define DP_MAX_DOWNSTREAM_PORTS 0x10
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#define DP_LINK_CONFIGURATION_SIZE 9
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struct intel_dp {
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struct intel_encoder base;
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uint32_t output_reg;
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uint32_t DP;
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uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
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bool has_audio;
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enum hdmi_force_audio force_audio;
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enum port port;
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uint32_t color_range;
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uint8_t link_bw;
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uint8_t lane_count;
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uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
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uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
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struct i2c_adapter adapter;
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struct i2c_algo_dp_aux_data algo;
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bool is_pch_edp;
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uint8_t train_set[4];
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int panel_power_up_delay;
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int panel_power_down_delay;
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int panel_power_cycle_delay;
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int backlight_on_delay;
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int backlight_off_delay;
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struct drm_display_mode *panel_fixed_mode; /* for eDP */
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struct delayed_work panel_vdd_work;
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bool want_panel_vdd;
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struct edid *edid; /* cached EDID for eDP */
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int edid_mode_count;
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};
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static inline struct drm_crtc *
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intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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return dev_priv->pipe_to_crtc_mapping[pipe];
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}
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static inline struct drm_crtc *
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intel_get_crtc_for_plane(struct drm_device *dev, int plane)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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return dev_priv->plane_to_crtc_mapping[plane];
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}
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struct intel_unpin_work {
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struct work_struct work;
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struct drm_device *dev;
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struct drm_i915_gem_object *old_fb_obj;
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struct drm_i915_gem_object *pending_flip_obj;
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struct drm_pending_vblank_event *event;
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int pending;
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bool enable_stall_check;
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};
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struct intel_fbc_work {
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struct delayed_work work;
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struct drm_crtc *crtc;
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struct drm_framebuffer *fb;
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int interval;
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};
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int intel_connector_update_modes(struct drm_connector *connector,
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struct edid *edid);
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int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
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extern void intel_attach_force_audio_property(struct drm_connector *connector);
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extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
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extern void intel_crt_init(struct drm_device *dev);
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extern void intel_hdmi_init(struct drm_device *dev,
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int sdvox_reg, enum port port);
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extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
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extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
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extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
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bool is_sdvob);
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extern void intel_dvo_init(struct drm_device *dev);
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extern void intel_tv_init(struct drm_device *dev);
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extern void intel_mark_busy(struct drm_device *dev);
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extern void intel_mark_idle(struct drm_device *dev);
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extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
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extern void intel_mark_fb_idle(struct drm_i915_gem_object *obj);
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extern bool intel_lvds_init(struct drm_device *dev);
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extern void intel_dp_init(struct drm_device *dev, int output_reg,
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enum port port);
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void
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intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode);
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extern bool intel_dpd_is_edp(struct drm_device *dev);
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extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
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extern int intel_edp_target_clock(struct intel_encoder *,
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struct drm_display_mode *mode);
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extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
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extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
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extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
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enum plane plane);
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/* intel_panel.c */
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extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
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struct drm_display_mode *adjusted_mode);
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extern void intel_pch_panel_fitting(struct drm_device *dev,
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int fitting_mode,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode);
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extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
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extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
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extern int intel_panel_setup_backlight(struct drm_device *dev);
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extern void intel_panel_enable_backlight(struct drm_device *dev,
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enum pipe pipe);
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extern void intel_panel_disable_backlight(struct drm_device *dev);
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extern void intel_panel_destroy_backlight(struct drm_device *dev);
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extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
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struct intel_set_config {
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struct drm_encoder **save_connector_encoders;
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struct drm_crtc **save_encoder_crtcs;
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bool fb_changed;
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bool mode_changed;
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};
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extern bool intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
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int x, int y, struct drm_framebuffer *old_fb);
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extern void intel_modeset_disable(struct drm_device *dev);
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extern void intel_crtc_load_lut(struct drm_crtc *crtc);
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extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
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extern void intel_encoder_noop(struct drm_encoder *encoder);
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extern void intel_encoder_destroy(struct drm_encoder *encoder);
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extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
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extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
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extern void intel_connector_dpms(struct drm_connector *, int mode);
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extern bool intel_connector_get_hw_state(struct intel_connector *connector);
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extern void intel_modeset_check_state(struct drm_device *dev);
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static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
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{
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return to_intel_connector(connector)->encoder;
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}
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extern void intel_connector_attach_encoder(struct intel_connector *connector,
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struct intel_encoder *encoder);
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extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
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extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
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struct drm_crtc *crtc);
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int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
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extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
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struct intel_load_detect_pipe {
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struct drm_framebuffer *release_fb;
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bool load_detect_temp;
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int dpms_mode;
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};
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extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
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struct drm_display_mode *mode,
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struct intel_load_detect_pipe *old);
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extern void intel_release_load_detect_pipe(struct drm_connector *connector,
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struct intel_load_detect_pipe *old);
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extern void intelfb_restore(void);
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extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
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|
u16 blue, int regno);
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extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
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|
u16 *blue, int regno);
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extern void intel_enable_clock_gating(struct drm_device *dev);
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|
|
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extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
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|
struct drm_i915_gem_object *obj,
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|
struct intel_ring_buffer *pipelined);
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|
extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
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|
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extern int intel_framebuffer_init(struct drm_device *dev,
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|
struct intel_framebuffer *ifb,
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|
struct drm_mode_fb_cmd2 *mode_cmd,
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|
struct drm_i915_gem_object *obj);
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|
extern int intel_fbdev_init(struct drm_device *dev);
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|
extern void intel_fbdev_fini(struct drm_device *dev);
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|
extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
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|
extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
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|
extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
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|
extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
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|
|
|
extern void intel_setup_overlay(struct drm_device *dev);
|
|
extern void intel_cleanup_overlay(struct drm_device *dev);
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|
extern int intel_overlay_switch_off(struct intel_overlay *overlay);
|
|
extern int intel_overlay_put_image(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
extern int intel_overlay_attrs(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
|
|
extern void intel_fb_output_poll_changed(struct drm_device *dev);
|
|
extern void intel_fb_restore_mode(struct drm_device *dev);
|
|
|
|
extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
|
|
bool state);
|
|
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
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|
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
|
|
|
|
extern void intel_init_clock_gating(struct drm_device *dev);
|
|
extern void intel_write_eld(struct drm_encoder *encoder,
|
|
struct drm_display_mode *mode);
|
|
extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
|
|
extern void intel_prepare_ddi(struct drm_device *dev);
|
|
extern void hsw_fdi_link_train(struct drm_crtc *crtc);
|
|
extern void intel_ddi_init(struct drm_device *dev, enum port port);
|
|
|
|
/* For use by IVB LP watermark workaround in intel_sprite.c */
|
|
extern void intel_update_watermarks(struct drm_device *dev);
|
|
extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
|
|
uint32_t sprite_width,
|
|
int pixel_size);
|
|
extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
|
|
struct drm_display_mode *mode);
|
|
|
|
extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
|
|
extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
|
|
|
|
/* Power-related functions, located in intel_pm.c */
|
|
extern void intel_init_pm(struct drm_device *dev);
|
|
/* FBC */
|
|
extern bool intel_fbc_enabled(struct drm_device *dev);
|
|
extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
|
|
extern void intel_update_fbc(struct drm_device *dev);
|
|
/* IPS */
|
|
extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
|
|
extern void intel_gpu_ips_teardown(void);
|
|
|
|
extern void intel_init_power_wells(struct drm_device *dev);
|
|
extern void intel_enable_gt_powersave(struct drm_device *dev);
|
|
extern void intel_disable_gt_powersave(struct drm_device *dev);
|
|
extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
|
|
extern void ironlake_teardown_rc6(struct drm_device *dev);
|
|
|
|
extern void intel_enable_ddi(struct intel_encoder *encoder);
|
|
extern void intel_disable_ddi(struct intel_encoder *encoder);
|
|
extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
|
|
enum pipe *pipe);
|
|
extern void intel_ddi_mode_set(struct drm_encoder *encoder,
|
|
struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode);
|
|
extern void intel_ddi_pll_init(struct drm_device *dev);
|
|
extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);
|
|
extern void intel_ddi_disable_pipe_func(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe);
|
|
extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
|
|
extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
|
|
extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
|
|
extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
|
|
extern void intel_ddi_pre_enable(struct intel_encoder *intel_encoder);
|
|
extern void intel_ddi_post_disable(struct intel_encoder *intel_encoder);
|
|
extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
|
|
|
|
#endif /* __INTEL_DRV_H__ */
|