forked from Minki/linux
adbc3695d9
Add initial dtsi files to support Marvell Armada 3700 SoC with Cortex-A53 CPUs. There are two members in this family: the Armada 3710 (Single CPU) and the Armada 3720 (Dual CPUs). It also adds a dts file for the Marvell Armada 3720 DB board. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
132 lines
3.8 KiB
Plaintext
132 lines
3.8 KiB
Plaintext
/*
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* Device Tree Include file for Marvell Armada 37xx family of SoCs.
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*
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* Copyright (C) 2016 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Marvell Armada 37xx SoC";
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compatible = "marvell,armada3700";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0>;
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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internal-regs {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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/* 32M internal register @ 0xd000_0000 */
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ranges = <0x0 0x0 0xd0000000 0x2000000>;
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uart0: serial@12000 {
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compatible = "marvell,armada-3700-uart";
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reg = <0x12000 0x400>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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usb3@58000 {
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compatible = "generic-xhci";
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reg = <0x58000 0x4000>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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sata@e0000 {
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compatible = "marvell,armada-3700-ahci";
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reg = <0xe0000 0x2000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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gic: interrupt-controller@1d00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x1d00000 0x10000>, /* GICD */
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<0x1d40000 0x40000>; /* GICR */
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};
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};
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};
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};
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