ec73276204
Depending on the prior state of the controller, the PLL reset may not be pulsed. Clear the register bit and set it after a small delay to ensure that the PLL is really reset. Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Eric Yuen <eyuen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> |
||
|---|---|---|
| .. | ||
| Kconfig | ||
| Makefile | ||
| pci-dra7xx.c | ||
| pci-exynos.c | ||
| pci-host-generic.c | ||
| pci-imx6.c | ||
| pci-mvebu.c | ||
| pci-rcar-gen2.c | ||
| pci-tegra.c | ||
| pcie-designware.c | ||
| pcie-designware.h | ||
| pcie-rcar.c | ||
| pcie-spear13xx.c | ||