forked from Minki/linux
bef4a0ab98
patches, both new drivers and fixes to existing. A high percentage of these are for Samsung platforms like Exynos. Core framework fixes and some new features like automagical clock re-parenting round out the patches. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJSLkImAAoJEDqPOy9afJhJOjsP/Ri26AW7XB9pPWJRSU9REBZA 31wxcFo2T+PNir9duwDwjFBFycC3MisaKFlg7D134M+7txbYqm1TRvfu9OEDxpSP 4b/Yl6TarN4dhCN2R+BREO8PnxCBVpspDcsdh6Esuwuet2xUom3UtN8yvSjhPP/u qGNmXQYXyQy4fom5r+GsDVW+HIhLkaX9b0fYc9EN/bqfgv94PMZAxAxsK9CroAGZ 0m0g9ZXw9iSvVfz+iQEqPINtvpTLHk0FGyimoSR7kvW4o4o47tVtLEWp7VjG6mr5 zvBsycaQq6NgxPu96iUWWhsO9Uj2I7/7JgidXF7r+wvEFs1mcgZtkkirSA/n4zUN C8a87rvQrZRLr+xXhVuqiVHCgCY8vXoHqkWg6SrZ62ORL8C7uYRpog5SEe2ZzLJX l5uGAsDM6el+Uc/YviCPoZbeFr3h3CQvvFo8+i2eN0v/Phf30rq4lotBvpQj894G ngEIMj+D8wshdYSF2dNJ0rLnkLHTgCbiA28L6Cl5TRzRMj3Uaj9aT3cmoLUnimZu 7F7nWU4Iu/vzQKCTQ+eTvwxXJqIlE0JeVbJilqH1f2a68JdXP1LOId+2w/CP8gqQ i2odj6JHMgBzM9rNs+y0Ir9X/bXIVi6F341c19Nl15srEiLLl8xQIpcPDaI/Kvzs pefYgF2yS5AZAW3ac90r =5GfA -----END PGP SIGNATURE----- Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux Pull clock framework changes from Michael Turquette: "The common clk framework changes for 3.12 are dominated by clock driver patches, both new drivers and fixes to existing. A high percentage of these are for Samsung platforms like Exynos. Core framework fixes and some new features like automagical clock re-parenting round out the patches" * tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits) clk: only call get_parent if there is one clk: samsung: exynos5250: Simplify registration of PLL rate tables clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 clk: samsung: exynos4: Register PLL rate tables for Exynos4210 clk: samsung: exynos4: Reorder registration of mout_vpllsrc clk: samsung: pll: Add support for rate configuration of PLL46xx clk: samsung: pll: Use new registration method for PLL46xx clk: samsung: pll: Add support for rate configuration of PLL45xx clk: samsung: pll: Use new registration method for PLL45xx clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls clk: samsung: exynos4: Remove checks for DT node clk: samsung: exynos4: Remove unused static clkdev aliases clk: samsung: Modify _get_rate() helper to use __clk_lookup() clk: samsung: exynos4: Use separate aliases for cpufreq related clocks clocksource: samsung_pwm_timer: Get clock from device tree ARM: dts: exynos4: Specify PWM clocks in PWM node pwm: samsung: Update DT bindings documentation to cover clocks clk: Move symbol export to proper location clk: fix new_parent dereference before null check clk: wm831x: Initialise wm831x pointer on init ...
52 lines
2.2 KiB
Plaintext
52 lines
2.2 KiB
Plaintext
* Samsung PWM timers
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Samsung SoCs contain PWM timer blocks which can be used for system clock source
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and clock event timers, as well as to drive SoC outputs with PWM signal. Each
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PWM timer block provides 5 PWM channels (not all of them can drive physical
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outputs - see SoC and board manual).
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Be aware that the clocksource driver supports only uniprocessor systems.
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Required properties:
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- compatible : should be one of following:
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samsung,s3c2410-pwm - for 16-bit timers present on S3C24xx SoCs
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samsung,s3c6400-pwm - for 32-bit timers present on S3C64xx SoCs
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samsung,s5p6440-pwm - for 32-bit timers present on S5P64x0 SoCs
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samsung,s5pc100-pwm - for 32-bit timers present on S5PC100, S5PV210,
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Exynos4210 rev0 SoCs
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samsung,exynos4210-pwm - for 32-bit timers present on Exynos4210,
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Exynos4x12 and Exynos5250 SoCs
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- reg: base address and size of register area
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- interrupts: list of timer interrupts (one interrupt per timer, starting at
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timer 0)
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- clock-names: should contain all following required clock names:
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- "timers" - PWM base clock used to generate PWM signals,
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and any subset of following optional clock names:
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- "pwm-tclk0" - first external PWM clock source,
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- "pwm-tclk1" - second external PWM clock source.
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Note that not all IP variants allow using all external clock sources.
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Refer to SoC documentation to learn which clock source configurations
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are available.
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- clocks: should contain clock specifiers of all clocks, which input names
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have been specified in clock-names property, in same order.
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- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
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the cells format. The only third cell flag supported by this binding is
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PWM_POLARITY_INVERTED.
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Optional properties:
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- samsung,pwm-outputs: list of PWM channels used as PWM outputs on particular
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platform - an array of up to 5 elements being indices of PWM channels
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(from 0 to 4), the order does not matter.
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Example:
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pwm@7f006000 {
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compatible = "samsung,s3c6400-pwm";
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reg = <0x7f006000 0x1000>;
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interrupt-parent = <&vic0>;
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interrupts = <23>, <24>, <25>, <27>, <28>;
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clocks = <&clock 67>;
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clock-names = "timers";
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samsung,pwm-outputs = <0>, <1>;
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#pwm-cells = <3>;
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}
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