forked from Minki/linux
a000b8c1e3
The registers in the GRLIB port of the controller are 32-bit and in big endian byte order. The PRELOW and PREHIGH registers are merged into one register. The subsequent registers have their offset decreased accordingly. Hence the register access needs to be handled in a non-standard manner using custom getreg and setreg functions. Add setreg and getreg functions for different register widths and let oc_setreg and oc_getreg use function pointers to call the appropriate functions. A type is added as the data of the of match table entries. A new entry with a different compatible string is added to the table. The type of that entry triggers usage of the custom grlib functions by setting the setreg and getreg function pointers. Signed-off-by: Andreas Larsson <andreas@gaisler.com> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
34 lines
913 B
Plaintext
34 lines
913 B
Plaintext
Device tree configuration for i2c-ocores
|
|
|
|
Required properties:
|
|
- compatible : "opencores,i2c-ocores" or "aeroflexgaisler,i2cmst"
|
|
- reg : bus address start and address range size of device
|
|
- interrupts : interrupt number
|
|
- clock-frequency : frequency of bus clock in Hz
|
|
- #address-cells : should be <1>
|
|
- #size-cells : should be <0>
|
|
|
|
Optional properties:
|
|
- reg-shift : device register offsets are shifted by this value
|
|
- reg-io-width : io register width in bytes (1, 2 or 4)
|
|
- regstep : deprecated, use reg-shift above
|
|
|
|
Example:
|
|
|
|
i2c0: ocores@a0000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "opencores,i2c-ocores";
|
|
reg = <0xa0000000 0x8>;
|
|
interrupts = <10>;
|
|
clock-frequency = <20000000>;
|
|
|
|
reg-shift = <0>; /* 8 bit registers */
|
|
reg-io-width = <1>; /* 8 bit read/write */
|
|
|
|
dummy@60 {
|
|
compatible = "dummy";
|
|
reg = <0x60>;
|
|
};
|
|
};
|