b84b4c9a68
In order to support new EASRC and simplify the code structure, We decide to share the common structure between them. This bring a problem that EASRC accept format directly from devicetree, but ASRC accept width from devicetree. In order to align with new ESARC, we add new property fsl,asrc-format. The fsl,asrc-format can replace the fsl,asrc-width, then driver can accept format from devicetree, don't need to convert it to format through width. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/e7acbde4b26a82b674a4091515a219e09f847eac.1587038908.git.shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
81 lines
2.9 KiB
Plaintext
81 lines
2.9 KiB
Plaintext
Freescale Asynchronous Sample Rate Converter (ASRC) Controller
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The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a
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signal associated with an input clock into a signal associated with a different
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output clock. The driver currently works as a Front End of DPCM with other Back
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Ends Audio controller such as ESAI, SSI and SAI. It has three pairs to support
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three substreams within totally 10 channels.
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Required properties:
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- compatible : Compatible list, should contain one of the following
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compatibles:
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"fsl,imx35-asrc",
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"fsl,imx53-asrc",
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"fsl,imx8qm-asrc",
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"fsl,imx8qxp-asrc",
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- reg : Offset and length of the register set for the device.
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- interrupts : Contains the spdif interrupt.
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- dmas : Generic dma devicetree binding as described in
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Documentation/devicetree/bindings/dma/dma.txt.
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- dma-names : Contains "rxa", "rxb", "rxc", "txa", "txb" and "txc".
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- clocks : Contains an entry for each entry in clock-names.
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- clock-names : Contains the following entries
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"mem" Peripheral access clock to access registers.
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"ipg" Peripheral clock to driver module.
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"asrck_<0-f>" Clock sources for input and output clock.
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"spba" The spba clock is required when ASRC is placed as a
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bus slave of the Shared Peripheral Bus and when two
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or more bus masters (CPU, DMA or DSP) try to access
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it. This property is optional depending on the SoC
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design.
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- fsl,asrc-rate : Defines a mutual sample rate used by DPCM Back Ends.
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- fsl,asrc-width : Defines a mutual sample width used by DPCM Back Ends.
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- fsl,asrc-clk-map : Defines clock map used in driver. which is required
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by imx8qm/imx8qxp platform
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<0> - select the map for asrc0 in imx8qm/imx8qxp
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<1> - select the map for asrc1 in imx8qm/imx8qxp
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Optional properties:
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- big-endian : If this property is absent, the little endian mode
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will be in use as default. Otherwise, the big endian
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mode will be in use for all the device registers.
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- fsl,asrc-format : Defines a mutual sample format used by DPCM Back
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Ends, which can replace the fsl,asrc-width.
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The value is 2 (S16_LE), or 6 (S24_LE).
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Example:
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asrc: asrc@2034000 {
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compatible = "fsl,imx53-asrc";
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reg = <0x02034000 0x4000>;
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interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 107>, <&clks 107>, <&clks 0>,
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<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
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<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
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<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
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<&clks 107>, <&clks 0>, <&clks 0>;
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clock-names = "mem", "ipg", "asrck0",
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"asrck_1", "asrck_2", "asrck_3", "asrck_4",
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"asrck_5", "asrck_6", "asrck_7", "asrck_8",
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"asrck_9", "asrck_a", "asrck_b", "asrck_c",
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"asrck_d", "asrck_e", "asrck_f";
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dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
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<&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
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dma-names = "rxa", "rxb", "rxc",
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"txa", "txb", "txc";
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fsl,asrc-rate = <48000>;
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fsl,asrc-width = <16>;
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};
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