forked from Minki/linux
eb740b5f3e
Original EEH implementation depends on struct pci_dn heavily. However, EEH shouldn't depend on that actually because EEH needn't share much information with other PCI components. That's to say, EEH should have worked independently. The patch introduces struct eeh_dev so that EEH core components needn't be working based on struct pci_dn in future. Also, struct pci_dn, struct eeh_dev instances are created in dynamic fasion and the binding with EEH device, OF node, PCI device is implemented as well. The EEH devices are created after PHBs are detected and initialized, but PCI emunation hasn't started yet. Apart from that, PHB might be created dynamically through DLPAR component and the EEH devices should be creatd as well. Another case might be OF node is created dynamically by DR (Dynamic Reconfiguration), which has been defined by PAPR. For those OF nodes created by DR, EEH devices should be also created accordingly. The binding between EEH device and OF node is done while the EEH device is initially created. The binding between EEH device and PCI device should be done after PCI emunation is done. Besides, PCI hotplug also needs the binding so that the EEH devices could be traced from the newly coming PCI buses or PCI devices. Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
301 lines
7.1 KiB
C
301 lines
7.1 KiB
C
/*
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* Copyright (C) 2001 Dave Engebretsen, IBM Corporation
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* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* RTAS specific routines for PCI.
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*
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* Based on code from pci.c, chrp_pci.c and pSeries_pci.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/threads.h>
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#include <linux/pci.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/irq.h>
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#include <asm/prom.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/iommu.h>
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#include <asm/rtas.h>
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#include <asm/mpic.h>
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#include <asm/ppc-pci.h>
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#include <asm/eeh.h>
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/* RTAS tokens */
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static int read_pci_config;
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static int write_pci_config;
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static int ibm_read_pci_config;
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static int ibm_write_pci_config;
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static inline int config_access_valid(struct pci_dn *dn, int where)
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{
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if (where < 256)
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return 1;
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if (where < 4096 && dn->pci_ext_config_space)
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return 1;
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return 0;
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}
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int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
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{
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int returnval = -1;
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unsigned long buid, addr;
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int ret;
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if (!pdn)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (!config_access_valid(pdn, where))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
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buid = pdn->phb->buid;
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if (buid) {
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ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval,
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addr, BUID_HI(buid), BUID_LO(buid), size);
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} else {
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ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size);
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}
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*val = returnval;
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if (ret)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (returnval == EEH_IO_ERROR_VALUE(size) &&
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eeh_dn_check_failure (pdn->node, NULL))
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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static int rtas_pci_read_config(struct pci_bus *bus,
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unsigned int devfn,
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int where, int size, u32 *val)
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{
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struct device_node *busdn, *dn;
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busdn = pci_bus_to_OF_node(bus);
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/* Search only direct children of the bus */
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for (dn = busdn->child; dn; dn = dn->sibling) {
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struct pci_dn *pdn = PCI_DN(dn);
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if (pdn && pdn->devfn == devfn
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&& of_device_is_available(dn))
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return rtas_read_config(pdn, where, size, val);
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}
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val)
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{
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unsigned long buid, addr;
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int ret;
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if (!pdn)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (!config_access_valid(pdn, where))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
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buid = pdn->phb->buid;
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if (buid) {
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ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr,
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BUID_HI(buid), BUID_LO(buid), size, (ulong) val);
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} else {
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ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val);
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}
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if (ret)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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static int rtas_pci_write_config(struct pci_bus *bus,
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unsigned int devfn,
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int where, int size, u32 val)
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{
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struct device_node *busdn, *dn;
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busdn = pci_bus_to_OF_node(bus);
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/* Search only direct children of the bus */
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for (dn = busdn->child; dn; dn = dn->sibling) {
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struct pci_dn *pdn = PCI_DN(dn);
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if (pdn && pdn->devfn == devfn
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&& of_device_is_available(dn))
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return rtas_write_config(pdn, where, size, val);
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}
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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static struct pci_ops rtas_pci_ops = {
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.read = rtas_pci_read_config,
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.write = rtas_pci_write_config,
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};
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static int is_python(struct device_node *dev)
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{
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const char *model = of_get_property(dev, "model", NULL);
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if (model && strstr(model, "Python"))
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return 1;
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return 0;
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}
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static void python_countermeasures(struct device_node *dev)
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{
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struct resource registers;
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void __iomem *chip_regs;
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volatile u32 val;
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if (of_address_to_resource(dev, 0, ®isters)) {
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printk(KERN_ERR "Can't get address for Python workarounds !\n");
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return;
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}
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/* Python's register file is 1 MB in size. */
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chip_regs = ioremap(registers.start & ~(0xfffffUL), 0x100000);
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/*
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* Firmware doesn't always clear this bit which is critical
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* for good performance - Anton
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*/
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#define PRG_CL_RESET_VALID 0x00010000
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val = in_be32(chip_regs + 0xf6030);
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if (val & PRG_CL_RESET_VALID) {
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printk(KERN_INFO "Python workaround: ");
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val &= ~PRG_CL_RESET_VALID;
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out_be32(chip_regs + 0xf6030, val);
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/*
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* We must read it back for changes to
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* take effect
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*/
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val = in_be32(chip_regs + 0xf6030);
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printk("reg0: %x\n", val);
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}
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iounmap(chip_regs);
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}
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void __init init_pci_config_tokens (void)
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{
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read_pci_config = rtas_token("read-pci-config");
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write_pci_config = rtas_token("write-pci-config");
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ibm_read_pci_config = rtas_token("ibm,read-pci-config");
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ibm_write_pci_config = rtas_token("ibm,write-pci-config");
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}
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unsigned long __devinit get_phb_buid (struct device_node *phb)
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{
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struct resource r;
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if (ibm_read_pci_config == -1)
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return 0;
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if (of_address_to_resource(phb, 0, &r))
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return 0;
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return r.start;
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}
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static int phb_set_bus_ranges(struct device_node *dev,
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struct pci_controller *phb)
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{
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const int *bus_range;
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unsigned int len;
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bus_range = of_get_property(dev, "bus-range", &len);
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if (bus_range == NULL || len < 2 * sizeof(int)) {
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return 1;
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}
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phb->first_busno = bus_range[0];
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phb->last_busno = bus_range[1];
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return 0;
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}
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int __devinit rtas_setup_phb(struct pci_controller *phb)
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{
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struct device_node *dev = phb->dn;
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if (is_python(dev))
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python_countermeasures(dev);
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if (phb_set_bus_ranges(dev, phb))
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return 1;
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phb->ops = &rtas_pci_ops;
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phb->buid = get_phb_buid(dev);
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return 0;
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}
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void __init find_and_init_phbs(void)
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{
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struct device_node *node;
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struct pci_controller *phb;
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struct device_node *root = of_find_node_by_path("/");
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for_each_child_of_node(root, node) {
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if (node->type == NULL || (strcmp(node->type, "pci") != 0 &&
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strcmp(node->type, "pciex") != 0))
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continue;
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phb = pcibios_alloc_controller(node);
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if (!phb)
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continue;
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rtas_setup_phb(phb);
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pci_process_bridge_OF_ranges(phb, node, 0);
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isa_bridge_find_early(phb);
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}
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of_node_put(root);
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pci_devs_phb_init();
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/* Create EEH devices for all PHBs */
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eeh_dev_phb_init();
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/*
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* pci_probe_only and pci_assign_all_buses can be set via properties
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* in chosen.
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*/
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if (of_chosen) {
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const int *prop;
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prop = of_get_property(of_chosen,
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"linux,pci-probe-only", NULL);
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if (prop)
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pci_probe_only = *prop;
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#ifdef CONFIG_PPC32 /* Will be made generic soon */
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prop = of_get_property(of_chosen,
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"linux,pci-assign-all-buses", NULL);
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if (prop && *prop)
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pci_add_flags(PCI_REASSIGN_ALL_BUS);
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#endif /* CONFIG_PPC32 */
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}
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}
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