2d1611aff3
Before the GMAC on the Anarion chip can be used, the PHY interface selection must be configured with the DWMAC block in reset. This layer covers a block containing only two registers. Although it is possible to model this as a reset controller and use the "resets" property of stmmac, it's much more intuitive to include this in the glue layer instead. At this time only RGMII is supported, because it is the only mode which has been validated hardware-wise. Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Signed-off-by: David S. Miller <davem@davemloft.net>
28 lines
1.2 KiB
Makefile
28 lines
1.2 KiB
Makefile
obj-$(CONFIG_STMMAC_ETH) += stmmac.o
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stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \
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chain_mode.o dwmac_lib.o dwmac1000_core.o dwmac1000_dma.o \
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dwmac100_core.o dwmac100_dma.o enh_desc.o norm_desc.o \
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mmc_core.o stmmac_hwtstamp.o stmmac_ptp.o dwmac4_descs.o \
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dwmac4_dma.o dwmac4_lib.o dwmac4_core.o $(stmmac-y)
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# Ordering matters. Generic driver must be last.
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obj-$(CONFIG_STMMAC_PLATFORM) += stmmac-platform.o
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obj-$(CONFIG_DWMAC_ANARION) += dwmac-anarion.o
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obj-$(CONFIG_DWMAC_IPQ806X) += dwmac-ipq806x.o
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obj-$(CONFIG_DWMAC_LPC18XX) += dwmac-lpc18xx.o
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obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o dwmac-meson8b.o
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obj-$(CONFIG_DWMAC_OXNAS) += dwmac-oxnas.o
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obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o
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obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o
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obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o
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obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o
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obj-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o
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obj-$(CONFIG_DWMAC_SUN8I) += dwmac-sun8i.o
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obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o
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obj-$(CONFIG_DWMAC_GENERIC) += dwmac-generic.o
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stmmac-platform-objs:= stmmac_platform.o
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dwmac-altr-socfpga-objs := altr_tse_pcs.o dwmac-socfpga.o
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obj-$(CONFIG_STMMAC_PCI) += stmmac-pci.o
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stmmac-pci-objs:= stmmac_pci.o
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