forked from Minki/linux
e811f5ae19
The passed mode must not be modified by the operation, make it const. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
537 lines
15 KiB
C
537 lines
15 KiB
C
/*
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* Copyright © 2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Li Peng <peng.li@intel.com>
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*/
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#include <drm/drmP.h>
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#include <drm/drm.h>
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#include "psb_intel_drv.h"
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#include "psb_intel_reg.h"
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#include "psb_drv.h"
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#define HDMI_READ(reg) readl(hdmi_dev->regs + (reg))
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#define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg))
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#define HDMI_HCR 0x1000
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#define HCR_ENABLE_HDCP (1 << 5)
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#define HCR_ENABLE_AUDIO (1 << 2)
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#define HCR_ENABLE_PIXEL (1 << 1)
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#define HCR_ENABLE_TMDS (1 << 0)
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#define HDMI_HICR 0x1004
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#define HDMI_HSR 0x1008
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#define HDMI_HISR 0x100C
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#define HDMI_DETECT_HDP (1 << 0)
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#define HDMI_VIDEO_REG 0x3000
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#define HDMI_UNIT_EN (1 << 7)
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#define HDMI_MODE_OUTPUT (1 << 0)
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#define HDMI_HBLANK_A 0x3100
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#define HDMI_AUDIO_CTRL 0x4000
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#define HDMI_ENABLE_AUDIO (1 << 0)
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#define PCH_HTOTAL_B 0x3100
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#define PCH_HBLANK_B 0x3104
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#define PCH_HSYNC_B 0x3108
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#define PCH_VTOTAL_B 0x310C
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#define PCH_VBLANK_B 0x3110
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#define PCH_VSYNC_B 0x3114
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#define PCH_PIPEBSRC 0x311C
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#define PCH_PIPEB_DSL 0x3800
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#define PCH_PIPEB_SLC 0x3804
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#define PCH_PIPEBCONF 0x3808
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#define PCH_PIPEBSTAT 0x3824
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#define CDVO_DFT 0x5000
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#define CDVO_SLEWRATE 0x5004
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#define CDVO_STRENGTH 0x5008
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#define CDVO_RCOMP 0x500C
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#define DPLL_CTRL 0x6000
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#define DPLL_PDIV_SHIFT 16
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#define DPLL_PDIV_MASK (0xf << 16)
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#define DPLL_PWRDN (1 << 4)
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#define DPLL_RESET (1 << 3)
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#define DPLL_FASTEN (1 << 2)
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#define DPLL_ENSTAT (1 << 1)
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#define DPLL_DITHEN (1 << 0)
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#define DPLL_DIV_CTRL 0x6004
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#define DPLL_CLKF_MASK 0xffffffc0
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#define DPLL_CLKR_MASK (0x3f)
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#define DPLL_CLK_ENABLE 0x6008
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#define DPLL_EN_DISP (1 << 31)
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#define DPLL_SEL_HDMI (1 << 8)
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#define DPLL_EN_HDMI (1 << 1)
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#define DPLL_EN_VGA (1 << 0)
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#define DPLL_ADJUST 0x600C
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#define DPLL_STATUS 0x6010
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#define DPLL_UPDATE 0x6014
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#define DPLL_DFT 0x6020
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struct intel_range {
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int min, max;
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};
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struct oaktrail_hdmi_limit {
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struct intel_range vco, np, nr, nf;
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};
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struct oaktrail_hdmi_clock {
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int np;
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int nr;
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int nf;
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int dot;
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};
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#define VCO_MIN 320000
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#define VCO_MAX 1650000
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#define NP_MIN 1
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#define NP_MAX 15
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#define NR_MIN 1
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#define NR_MAX 64
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#define NF_MIN 2
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#define NF_MAX 4095
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static const struct oaktrail_hdmi_limit oaktrail_hdmi_limit = {
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.vco = { .min = VCO_MIN, .max = VCO_MAX },
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.np = { .min = NP_MIN, .max = NP_MAX },
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.nr = { .min = NR_MIN, .max = NR_MAX },
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.nf = { .min = NF_MIN, .max = NF_MAX },
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};
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static void oaktrail_hdmi_audio_enable(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
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HDMI_WRITE(HDMI_HCR, 0x67);
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HDMI_READ(HDMI_HCR);
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HDMI_WRITE(0x51a8, 0x10);
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HDMI_READ(0x51a8);
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HDMI_WRITE(HDMI_AUDIO_CTRL, 0x1);
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HDMI_READ(HDMI_AUDIO_CTRL);
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}
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static void oaktrail_hdmi_audio_disable(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
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HDMI_WRITE(0x51a8, 0x0);
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HDMI_READ(0x51a8);
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HDMI_WRITE(HDMI_AUDIO_CTRL, 0x0);
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HDMI_READ(HDMI_AUDIO_CTRL);
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HDMI_WRITE(HDMI_HCR, 0x47);
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HDMI_READ(HDMI_HCR);
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}
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static void oaktrail_hdmi_dpms(struct drm_encoder *encoder, int mode)
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{
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static int dpms_mode = -1;
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struct drm_device *dev = encoder->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
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u32 temp;
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if (dpms_mode == mode)
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return;
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if (mode != DRM_MODE_DPMS_ON)
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temp = 0x0;
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else
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temp = 0x99;
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dpms_mode = mode;
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HDMI_WRITE(HDMI_VIDEO_REG, temp);
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}
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static int oaktrail_hdmi_mode_valid(struct drm_connector *connector,
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struct drm_display_mode *mode)
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{
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if (mode->clock > 165000)
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return MODE_CLOCK_HIGH;
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if (mode->clock < 20000)
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return MODE_CLOCK_LOW;
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if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
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return MODE_NO_DBLESCAN;
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return MODE_OK;
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}
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static bool oaktrail_hdmi_mode_fixup(struct drm_encoder *encoder,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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return true;
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}
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static enum drm_connector_status
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oaktrail_hdmi_detect(struct drm_connector *connector, bool force)
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{
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enum drm_connector_status status;
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struct drm_device *dev = connector->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
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u32 temp;
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temp = HDMI_READ(HDMI_HSR);
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DRM_DEBUG_KMS("HDMI_HSR %x\n", temp);
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if ((temp & HDMI_DETECT_HDP) != 0)
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status = connector_status_connected;
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else
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status = connector_status_disconnected;
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return status;
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}
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static const unsigned char raw_edid[] = {
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0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x10, 0xac, 0x2f, 0xa0,
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0x53, 0x55, 0x33, 0x30, 0x16, 0x13, 0x01, 0x03, 0x0e, 0x3a, 0x24, 0x78,
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0xea, 0xe9, 0xf5, 0xac, 0x51, 0x30, 0xb4, 0x25, 0x11, 0x50, 0x54, 0xa5,
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0x4b, 0x00, 0x81, 0x80, 0xa9, 0x40, 0x71, 0x4f, 0xb3, 0x00, 0x01, 0x01,
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0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
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0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x46, 0x6c, 0x21, 0x00, 0x00, 0x1a,
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0x00, 0x00, 0x00, 0xff, 0x00, 0x47, 0x4e, 0x37, 0x32, 0x31, 0x39, 0x35,
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0x52, 0x30, 0x33, 0x55, 0x53, 0x0a, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x44,
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0x45, 0x4c, 0x4c, 0x20, 0x32, 0x37, 0x30, 0x39, 0x57, 0x0a, 0x20, 0x20,
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0x00, 0x00, 0x00, 0xfd, 0x00, 0x38, 0x4c, 0x1e, 0x53, 0x11, 0x00, 0x0a,
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0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x8d
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};
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static int oaktrail_hdmi_get_modes(struct drm_connector *connector)
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{
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struct drm_device *dev = connector->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct i2c_adapter *i2c_adap;
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struct edid *edid;
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struct drm_display_mode *mode, *t;
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int i = 0, ret = 0;
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i2c_adap = i2c_get_adapter(3);
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if (i2c_adap == NULL) {
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DRM_ERROR("No ddc adapter available!\n");
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edid = (struct edid *)raw_edid;
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} else {
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edid = (struct edid *)raw_edid;
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/* FIXME ? edid = drm_get_edid(connector, i2c_adap); */
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}
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if (edid) {
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drm_mode_connector_update_edid_property(connector, edid);
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ret = drm_add_edid_modes(connector, edid);
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connector->display_info.raw_edid = NULL;
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}
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/*
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* prune modes that require frame buffer bigger than stolen mem
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*/
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list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
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if ((mode->hdisplay * mode->vdisplay * 4) >= dev_priv->vram_stolen_size) {
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i++;
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drm_mode_remove(connector, mode);
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}
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}
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return ret - i;
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}
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static void oaktrail_hdmi_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct drm_device *dev = encoder->dev;
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oaktrail_hdmi_audio_enable(dev);
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return;
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}
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static void oaktrail_hdmi_destroy(struct drm_connector *connector)
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{
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return;
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}
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static const struct drm_encoder_helper_funcs oaktrail_hdmi_helper_funcs = {
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.dpms = oaktrail_hdmi_dpms,
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.mode_fixup = oaktrail_hdmi_mode_fixup,
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.prepare = psb_intel_encoder_prepare,
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.mode_set = oaktrail_hdmi_mode_set,
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.commit = psb_intel_encoder_commit,
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};
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static const struct drm_connector_helper_funcs
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oaktrail_hdmi_connector_helper_funcs = {
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.get_modes = oaktrail_hdmi_get_modes,
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.mode_valid = oaktrail_hdmi_mode_valid,
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.best_encoder = psb_intel_best_encoder,
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};
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static const struct drm_connector_funcs oaktrail_hdmi_connector_funcs = {
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.dpms = drm_helper_connector_dpms,
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.detect = oaktrail_hdmi_detect,
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.fill_modes = drm_helper_probe_single_connector_modes,
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.destroy = oaktrail_hdmi_destroy,
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};
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static void oaktrail_hdmi_enc_destroy(struct drm_encoder *encoder)
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{
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drm_encoder_cleanup(encoder);
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}
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static const struct drm_encoder_funcs oaktrail_hdmi_enc_funcs = {
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.destroy = oaktrail_hdmi_enc_destroy,
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};
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void oaktrail_hdmi_init(struct drm_device *dev,
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struct psb_intel_mode_device *mode_dev)
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{
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struct psb_intel_encoder *psb_intel_encoder;
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struct psb_intel_connector *psb_intel_connector;
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struct drm_connector *connector;
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struct drm_encoder *encoder;
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psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder), GFP_KERNEL);
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if (!psb_intel_encoder)
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return;
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psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector), GFP_KERNEL);
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if (!psb_intel_connector)
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goto failed_connector;
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connector = &psb_intel_connector->base;
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encoder = &psb_intel_encoder->base;
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drm_connector_init(dev, connector,
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&oaktrail_hdmi_connector_funcs,
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DRM_MODE_CONNECTOR_DVID);
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drm_encoder_init(dev, encoder,
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&oaktrail_hdmi_enc_funcs,
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DRM_MODE_ENCODER_TMDS);
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psb_intel_connector_attach_encoder(psb_intel_connector,
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psb_intel_encoder);
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psb_intel_encoder->type = INTEL_OUTPUT_HDMI;
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drm_encoder_helper_add(encoder, &oaktrail_hdmi_helper_funcs);
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drm_connector_helper_add(connector, &oaktrail_hdmi_connector_helper_funcs);
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connector->display_info.subpixel_order = SubPixelHorizontalRGB;
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connector->interlace_allowed = false;
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connector->doublescan_allowed = false;
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drm_sysfs_connector_add(connector);
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return;
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failed_connector:
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kfree(psb_intel_encoder);
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}
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static DEFINE_PCI_DEVICE_TABLE(hdmi_ids) = {
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080d) },
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{ 0 }
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};
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void oaktrail_hdmi_setup(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct pci_dev *pdev;
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struct oaktrail_hdmi_dev *hdmi_dev;
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int ret;
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pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x080d, NULL);
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if (!pdev)
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return;
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hdmi_dev = kzalloc(sizeof(struct oaktrail_hdmi_dev), GFP_KERNEL);
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if (!hdmi_dev) {
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dev_err(dev->dev, "failed to allocate memory\n");
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goto out;
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}
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ret = pci_enable_device(pdev);
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if (ret) {
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dev_err(dev->dev, "failed to enable hdmi controller\n");
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goto free;
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}
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hdmi_dev->mmio = pci_resource_start(pdev, 0);
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hdmi_dev->mmio_len = pci_resource_len(pdev, 0);
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hdmi_dev->regs = ioremap(hdmi_dev->mmio, hdmi_dev->mmio_len);
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if (!hdmi_dev->regs) {
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dev_err(dev->dev, "failed to map hdmi mmio\n");
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goto free;
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}
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hdmi_dev->dev = pdev;
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pci_set_drvdata(pdev, hdmi_dev);
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/* Initialize i2c controller */
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ret = oaktrail_hdmi_i2c_init(hdmi_dev->dev);
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if (ret)
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dev_err(dev->dev, "HDMI I2C initialization failed\n");
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dev_priv->hdmi_priv = hdmi_dev;
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oaktrail_hdmi_audio_disable(dev);
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return;
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free:
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kfree(hdmi_dev);
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out:
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return;
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}
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void oaktrail_hdmi_teardown(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
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struct pci_dev *pdev;
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if (hdmi_dev) {
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pdev = hdmi_dev->dev;
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pci_set_drvdata(pdev, NULL);
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oaktrail_hdmi_i2c_exit(pdev);
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iounmap(hdmi_dev->regs);
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kfree(hdmi_dev);
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pci_dev_put(pdev);
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}
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}
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/* save HDMI register state */
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void oaktrail_hdmi_save(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
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struct psb_state *regs = &dev_priv->regs.psb;
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struct psb_pipe *pipeb = &dev_priv->regs.pipe[1];
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int i;
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/* dpll */
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hdmi_dev->saveDPLL_CTRL = PSB_RVDC32(DPLL_CTRL);
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hdmi_dev->saveDPLL_DIV_CTRL = PSB_RVDC32(DPLL_DIV_CTRL);
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hdmi_dev->saveDPLL_ADJUST = PSB_RVDC32(DPLL_ADJUST);
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hdmi_dev->saveDPLL_UPDATE = PSB_RVDC32(DPLL_UPDATE);
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hdmi_dev->saveDPLL_CLK_ENABLE = PSB_RVDC32(DPLL_CLK_ENABLE);
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/* pipe B */
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pipeb->conf = PSB_RVDC32(PIPEBCONF);
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pipeb->src = PSB_RVDC32(PIPEBSRC);
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pipeb->htotal = PSB_RVDC32(HTOTAL_B);
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pipeb->hblank = PSB_RVDC32(HBLANK_B);
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pipeb->hsync = PSB_RVDC32(HSYNC_B);
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pipeb->vtotal = PSB_RVDC32(VTOTAL_B);
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pipeb->vblank = PSB_RVDC32(VBLANK_B);
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|
pipeb->vsync = PSB_RVDC32(VSYNC_B);
|
|
|
|
hdmi_dev->savePCH_PIPEBCONF = PSB_RVDC32(PCH_PIPEBCONF);
|
|
hdmi_dev->savePCH_PIPEBSRC = PSB_RVDC32(PCH_PIPEBSRC);
|
|
hdmi_dev->savePCH_HTOTAL_B = PSB_RVDC32(PCH_HTOTAL_B);
|
|
hdmi_dev->savePCH_HBLANK_B = PSB_RVDC32(PCH_HBLANK_B);
|
|
hdmi_dev->savePCH_HSYNC_B = PSB_RVDC32(PCH_HSYNC_B);
|
|
hdmi_dev->savePCH_VTOTAL_B = PSB_RVDC32(PCH_VTOTAL_B);
|
|
hdmi_dev->savePCH_VBLANK_B = PSB_RVDC32(PCH_VBLANK_B);
|
|
hdmi_dev->savePCH_VSYNC_B = PSB_RVDC32(PCH_VSYNC_B);
|
|
|
|
/* plane */
|
|
pipeb->cntr = PSB_RVDC32(DSPBCNTR);
|
|
pipeb->stride = PSB_RVDC32(DSPBSTRIDE);
|
|
pipeb->addr = PSB_RVDC32(DSPBBASE);
|
|
pipeb->surf = PSB_RVDC32(DSPBSURF);
|
|
pipeb->linoff = PSB_RVDC32(DSPBLINOFF);
|
|
pipeb->tileoff = PSB_RVDC32(DSPBTILEOFF);
|
|
|
|
/* cursor B */
|
|
regs->saveDSPBCURSOR_CTRL = PSB_RVDC32(CURBCNTR);
|
|
regs->saveDSPBCURSOR_BASE = PSB_RVDC32(CURBBASE);
|
|
regs->saveDSPBCURSOR_POS = PSB_RVDC32(CURBPOS);
|
|
|
|
/* save palette */
|
|
for (i = 0; i < 256; i++)
|
|
pipeb->palette[i] = PSB_RVDC32(PALETTE_B + (i << 2));
|
|
}
|
|
|
|
/* restore HDMI register state */
|
|
void oaktrail_hdmi_restore(struct drm_device *dev)
|
|
{
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
|
|
struct psb_state *regs = &dev_priv->regs.psb;
|
|
struct psb_pipe *pipeb = &dev_priv->regs.pipe[1];
|
|
int i;
|
|
|
|
/* dpll */
|
|
PSB_WVDC32(hdmi_dev->saveDPLL_CTRL, DPLL_CTRL);
|
|
PSB_WVDC32(hdmi_dev->saveDPLL_DIV_CTRL, DPLL_DIV_CTRL);
|
|
PSB_WVDC32(hdmi_dev->saveDPLL_ADJUST, DPLL_ADJUST);
|
|
PSB_WVDC32(hdmi_dev->saveDPLL_UPDATE, DPLL_UPDATE);
|
|
PSB_WVDC32(hdmi_dev->saveDPLL_CLK_ENABLE, DPLL_CLK_ENABLE);
|
|
DRM_UDELAY(150);
|
|
|
|
/* pipe */
|
|
PSB_WVDC32(pipeb->src, PIPEBSRC);
|
|
PSB_WVDC32(pipeb->htotal, HTOTAL_B);
|
|
PSB_WVDC32(pipeb->hblank, HBLANK_B);
|
|
PSB_WVDC32(pipeb->hsync, HSYNC_B);
|
|
PSB_WVDC32(pipeb->vtotal, VTOTAL_B);
|
|
PSB_WVDC32(pipeb->vblank, VBLANK_B);
|
|
PSB_WVDC32(pipeb->vsync, VSYNC_B);
|
|
|
|
PSB_WVDC32(hdmi_dev->savePCH_PIPEBSRC, PCH_PIPEBSRC);
|
|
PSB_WVDC32(hdmi_dev->savePCH_HTOTAL_B, PCH_HTOTAL_B);
|
|
PSB_WVDC32(hdmi_dev->savePCH_HBLANK_B, PCH_HBLANK_B);
|
|
PSB_WVDC32(hdmi_dev->savePCH_HSYNC_B, PCH_HSYNC_B);
|
|
PSB_WVDC32(hdmi_dev->savePCH_VTOTAL_B, PCH_VTOTAL_B);
|
|
PSB_WVDC32(hdmi_dev->savePCH_VBLANK_B, PCH_VBLANK_B);
|
|
PSB_WVDC32(hdmi_dev->savePCH_VSYNC_B, PCH_VSYNC_B);
|
|
|
|
PSB_WVDC32(pipeb->conf, PIPEBCONF);
|
|
PSB_WVDC32(hdmi_dev->savePCH_PIPEBCONF, PCH_PIPEBCONF);
|
|
|
|
/* plane */
|
|
PSB_WVDC32(pipeb->linoff, DSPBLINOFF);
|
|
PSB_WVDC32(pipeb->stride, DSPBSTRIDE);
|
|
PSB_WVDC32(pipeb->tileoff, DSPBTILEOFF);
|
|
PSB_WVDC32(pipeb->cntr, DSPBCNTR);
|
|
PSB_WVDC32(pipeb->surf, DSPBSURF);
|
|
|
|
/* cursor B */
|
|
PSB_WVDC32(regs->saveDSPBCURSOR_CTRL, CURBCNTR);
|
|
PSB_WVDC32(regs->saveDSPBCURSOR_POS, CURBPOS);
|
|
PSB_WVDC32(regs->saveDSPBCURSOR_BASE, CURBBASE);
|
|
|
|
/* restore palette */
|
|
for (i = 0; i < 256; i++)
|
|
PSB_WVDC32(pipeb->palette[i], PALETTE_B + (i << 2));
|
|
}
|