b70666934b
[Why]: Some active dongles have DP++ port and DP port at the same time. Current code doesn't cover DP++ case and processes as default DVI case, in which audio is disabled. Because of dual mode, DP case is also treat as DVI case for the other port. [How]: According DP 1.4 spec, add DP++ procedure similar with HDMI case. Also add None dongle type for DP case. Signed-off-by: Dale Zhao <dale.zhao@amd.com> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
153 lines
4.4 KiB
C
153 lines
4.4 KiB
C
/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_DPCD_DEFS_H__
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#define __DAL_DPCD_DEFS_H__
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#include <drm/drm_dp_helper.h>
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#ifndef DP_SINK_HW_REVISION_START // can remove this once the define gets into linux drm_dp_helper.h
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#define DP_SINK_HW_REVISION_START 0x409
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#endif
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enum dpcd_revision {
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DPCD_REV_10 = 0x10,
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DPCD_REV_11 = 0x11,
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DPCD_REV_12 = 0x12,
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DPCD_REV_13 = 0x13,
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DPCD_REV_14 = 0x14
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};
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/* these are the types stored at DOWNSTREAMPORT_PRESENT */
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enum dpcd_downstream_port_type {
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DOWNSTREAM_DP = 0,
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DOWNSTREAM_VGA,
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DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS,/* DVI, HDMI, DP++ */
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DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */
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};
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enum dpcd_link_test_patterns {
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LINK_TEST_PATTERN_NONE = 0,
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LINK_TEST_PATTERN_COLOR_RAMP,
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LINK_TEST_PATTERN_VERTICAL_BARS,
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LINK_TEST_PATTERN_COLOR_SQUARES
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};
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enum dpcd_test_color_format {
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TEST_COLOR_FORMAT_RGB = 0,
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TEST_COLOR_FORMAT_YCBCR422,
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TEST_COLOR_FORMAT_YCBCR444
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};
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enum dpcd_test_bit_depth {
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TEST_BIT_DEPTH_6 = 0,
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TEST_BIT_DEPTH_8,
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TEST_BIT_DEPTH_10,
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TEST_BIT_DEPTH_12,
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TEST_BIT_DEPTH_16
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};
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/* PHY (encoder) test patterns
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The order of test patterns follows DPCD register PHY_TEST_PATTERN (0x248)
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*/
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enum dpcd_phy_test_patterns {
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PHY_TEST_PATTERN_NONE = 0,
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PHY_TEST_PATTERN_D10_2,
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PHY_TEST_PATTERN_SYMBOL_ERROR,
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PHY_TEST_PATTERN_PRBS7,
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PHY_TEST_PATTERN_80BIT_CUSTOM,/* For DP1.2 only */
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PHY_TEST_PATTERN_CP2520_1,
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PHY_TEST_PATTERN_CP2520_2,
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PHY_TEST_PATTERN_CP2520_3, /* same as TPS4 */
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};
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enum dpcd_test_dyn_range {
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TEST_DYN_RANGE_VESA = 0,
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TEST_DYN_RANGE_CEA
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};
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enum dpcd_audio_test_pattern {
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AUDIO_TEST_PATTERN_OPERATOR_DEFINED = 0,/* direct HW translation */
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AUDIO_TEST_PATTERN_SAWTOOTH
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};
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enum dpcd_audio_sampling_rate {
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AUDIO_SAMPLING_RATE_32KHZ = 0,/* direct HW translation */
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AUDIO_SAMPLING_RATE_44_1KHZ,
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AUDIO_SAMPLING_RATE_48KHZ,
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AUDIO_SAMPLING_RATE_88_2KHZ,
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AUDIO_SAMPLING_RATE_96KHZ,
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AUDIO_SAMPLING_RATE_176_4KHZ,
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AUDIO_SAMPLING_RATE_192KHZ
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};
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enum dpcd_audio_channels {
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AUDIO_CHANNELS_1 = 0,/* direct HW translation */
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AUDIO_CHANNELS_2,
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AUDIO_CHANNELS_3,
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AUDIO_CHANNELS_4,
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AUDIO_CHANNELS_5,
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AUDIO_CHANNELS_6,
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AUDIO_CHANNELS_7,
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AUDIO_CHANNELS_8,
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AUDIO_CHANNELS_COUNT
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};
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enum dpcd_audio_test_pattern_periods {
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DPCD_AUDIO_TEST_PATTERN_PERIOD_NOTUSED = 0,/* direct HW translation */
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DPCD_AUDIO_TEST_PATTERN_PERIOD_3,
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DPCD_AUDIO_TEST_PATTERN_PERIOD_6,
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DPCD_AUDIO_TEST_PATTERN_PERIOD_12,
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DPCD_AUDIO_TEST_PATTERN_PERIOD_24,
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DPCD_AUDIO_TEST_PATTERN_PERIOD_48,
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DPCD_AUDIO_TEST_PATTERN_PERIOD_96,
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DPCD_AUDIO_TEST_PATTERN_PERIOD_192,
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DPCD_AUDIO_TEST_PATTERN_PERIOD_384,
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DPCD_AUDIO_TEST_PATTERN_PERIOD_768,
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DPCD_AUDIO_TEST_PATTERN_PERIOD_1536
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};
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/* This enum is for programming DPCD TRAINING_PATTERN_SET */
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enum dpcd_training_patterns {
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DPCD_TRAINING_PATTERN_VIDEOIDLE = 0,/* direct HW translation! */
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DPCD_TRAINING_PATTERN_1,
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DPCD_TRAINING_PATTERN_2,
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DPCD_TRAINING_PATTERN_3,
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DPCD_TRAINING_PATTERN_4 = 7
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};
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/* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus
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It defines the possible PSR states. */
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enum dpcd_psr_sink_states {
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PSR_SINK_STATE_INACTIVE = 0,
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PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SOURCE_TIMING = 1,
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PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB = 2,
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PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SINK_TIMING = 3,
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PSR_SINK_STATE_ACTIVE_CAPTURE_TIMING_RESYNC = 4,
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PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7,
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};
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#endif /* __DAL_DPCD_DEFS_H__ */
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