d98fb328ad
For encryption to work properly, the BSS index needs to be initialized for the WCID entry used for the interface. Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
234 lines
6.1 KiB
C
234 lines
6.1 KiB
C
/*
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* Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef __MT76x2_H
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#define __MT76x2_H
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/spinlock.h>
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#include <linux/skbuff.h>
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#include <linux/netdevice.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/mutex.h>
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#include <linux/bitops.h>
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#include <linux/kfifo.h>
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#define MT7662_FIRMWARE "mt7662.bin"
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#define MT7662_ROM_PATCH "mt7662_rom_patch.bin"
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#define MT7662_EEPROM_SIZE 512
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#define MT76x2_RX_RING_SIZE 256
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#define MT_RX_HEADROOM 32
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#define MT_MAX_CHAINS 2
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#define MT_CALIBRATE_INTERVAL HZ
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#define MT_MAX_VIFS 8
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#define MT_VIF_WCID(_n) (254 - ((_n) & 7))
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#include "mt76.h"
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#include "mt76x2_regs.h"
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#include "mt76x2_mac.h"
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#include "mt76x2_dfs.h"
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struct mt76x2_mcu {
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struct mutex mutex;
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wait_queue_head_t wait;
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struct sk_buff_head res_q;
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u32 msg_seq;
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};
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struct mt76x2_rx_freq_cal {
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s8 high_gain[MT_MAX_CHAINS];
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s8 rssi_offset[MT_MAX_CHAINS];
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s8 lna_gain;
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u32 mcu_gain;
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};
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struct mt76x2_calibration {
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struct mt76x2_rx_freq_cal rx;
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u8 agc_gain_init[MT_MAX_CHAINS];
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u8 agc_gain_cur[MT_MAX_CHAINS];
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int avg_rssi[MT_MAX_CHAINS];
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int avg_rssi_all;
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s8 agc_gain_adjust;
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s8 low_gain;
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u8 temp;
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bool init_cal_done;
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bool tssi_cal_done;
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bool tssi_comp_pending;
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bool dpd_cal_done;
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bool channel_cal_done;
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};
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struct mt76x2_dev {
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struct mt76_dev mt76; /* must be first */
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struct mac_address macaddr_list[8];
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struct mutex mutex;
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const u16 *beacon_offsets;
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unsigned long wcid_mask[128 / BITS_PER_LONG];
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int txpower_conf;
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int txpower_cur;
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u8 txdone_seq;
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DECLARE_KFIFO_PTR(txstatus_fifo, struct mt76x2_tx_status);
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struct mt76x2_mcu mcu;
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struct sk_buff *rx_head;
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struct tasklet_struct tx_tasklet;
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struct tasklet_struct pre_tbtt_tasklet;
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struct delayed_work cal_work;
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struct delayed_work mac_work;
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u32 aggr_stats[32];
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struct mt76_wcid global_wcid;
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struct mt76_wcid __rcu *wcid[128];
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spinlock_t irq_lock;
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u32 irqmask;
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struct sk_buff *beacons[8];
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u8 beacon_mask;
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u8 beacon_data_mask;
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u32 rxfilter;
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u16 chainmask;
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struct mt76x2_calibration cal;
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s8 target_power;
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s8 target_power_delta[2];
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struct mt76_rate_power rate_power;
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bool enable_tpc;
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u8 coverage_class;
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u8 slottime;
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struct mt76x2_dfs_pattern_detector dfs_pd;
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};
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struct mt76x2_vif {
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u8 idx;
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struct mt76_wcid group_wcid;
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};
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struct mt76x2_sta {
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struct mt76_wcid wcid; /* must be first */
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struct mt76x2_vif *vif;
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struct mt76x2_tx_status status;
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int n_frames;
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};
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static inline bool is_mt7612(struct mt76x2_dev *dev)
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{
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return mt76_chip(&dev->mt76) == 0x7612;
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}
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void mt76x2_set_irq_mask(struct mt76x2_dev *dev, u32 clear, u32 set);
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static inline void mt76x2_irq_enable(struct mt76x2_dev *dev, u32 mask)
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{
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mt76x2_set_irq_mask(dev, 0, mask);
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}
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static inline void mt76x2_irq_disable(struct mt76x2_dev *dev, u32 mask)
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{
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mt76x2_set_irq_mask(dev, mask, 0);
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}
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extern const struct ieee80211_ops mt76x2_ops;
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struct mt76x2_dev *mt76x2_alloc_device(struct device *pdev);
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int mt76x2_register_device(struct mt76x2_dev *dev);
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void mt76x2_init_debugfs(struct mt76x2_dev *dev);
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irqreturn_t mt76x2_irq_handler(int irq, void *dev_instance);
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void mt76x2_phy_power_on(struct mt76x2_dev *dev);
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int mt76x2_init_hardware(struct mt76x2_dev *dev);
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void mt76x2_stop_hardware(struct mt76x2_dev *dev);
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int mt76x2_eeprom_init(struct mt76x2_dev *dev);
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int mt76x2_apply_calibration_data(struct mt76x2_dev *dev, int channel);
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void mt76x2_set_tx_ackto(struct mt76x2_dev *dev);
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void mt76x2_phy_set_antenna(struct mt76x2_dev *dev);
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int mt76x2_phy_start(struct mt76x2_dev *dev);
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int mt76x2_phy_set_channel(struct mt76x2_dev *dev,
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struct cfg80211_chan_def *chandef);
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int mt76x2_phy_get_rssi(struct mt76x2_dev *dev, s8 rssi, int chain);
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void mt76x2_phy_calibrate(struct work_struct *work);
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void mt76x2_phy_set_txpower(struct mt76x2_dev *dev);
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int mt76x2_mcu_init(struct mt76x2_dev *dev);
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int mt76x2_mcu_set_channel(struct mt76x2_dev *dev, u8 channel, u8 bw,
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u8 bw_index, bool scan);
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int mt76x2_mcu_set_radio_state(struct mt76x2_dev *dev, bool on);
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int mt76x2_mcu_load_cr(struct mt76x2_dev *dev, u8 type, u8 temp_level,
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u8 channel);
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int mt76x2_mcu_cleanup(struct mt76x2_dev *dev);
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int mt76x2_dma_init(struct mt76x2_dev *dev);
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void mt76x2_dma_cleanup(struct mt76x2_dev *dev);
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void mt76x2_cleanup(struct mt76x2_dev *dev);
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int mt76x2_tx_queue_mcu(struct mt76x2_dev *dev, enum mt76_txq_id qid,
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struct sk_buff *skb, int cmd, int seq);
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void mt76x2_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
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struct sk_buff *skb);
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void mt76x2_tx_complete(struct mt76x2_dev *dev, struct sk_buff *skb);
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int mt76x2_tx_prepare_skb(struct mt76_dev *mdev, void *txwi,
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struct sk_buff *skb, struct mt76_queue *q,
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struct mt76_wcid *wcid, struct ieee80211_sta *sta,
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u32 *tx_info);
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void mt76x2_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue *q,
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struct mt76_queue_entry *e, bool flush);
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void mt76x2_pre_tbtt_tasklet(unsigned long arg);
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void mt76x2_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
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void mt76x2_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
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struct sk_buff *skb);
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void mt76x2_sta_ps(struct mt76_dev *dev, struct ieee80211_sta *sta, bool ps);
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void mt76x2_update_channel(struct mt76_dev *mdev);
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s8 mt76x2_tx_get_max_txpwr_adj(struct mt76x2_dev *dev,
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const struct ieee80211_tx_rate *rate);
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s8 mt76x2_tx_get_txpwr_adj(struct mt76x2_dev *dev, s8 txpwr, s8 max_txpwr_adj);
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void mt76x2_tx_set_txpwr_auto(struct mt76x2_dev *dev, s8 txpwr);
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#endif
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