forked from Minki/linux
e745f992cf
In normal operation pll_u is under hardware control and has a fixed rate of 480MHz. Hardware will turn on pll_u on whenever any of the XUSB powerdomains is on. From a software point of view we model this is if pll_u is always on using a fixed rate clock. However the bootloader might or might not have configured pll_u this way. So we will check the current state of pll_u at boot and reconfigure it if required. There are 3 possiblities at kernel boot: 1) pll_u is under hardware control: do nothing 2) pll_u is under hardware control and enabled: enable hardware control 3) pll_u is disabled: enable pll_u and enable hardware control In all cases we also check if UTMIPLL is under hardware control at boot and configure it for hardware control if that is not the case. The same is done during SC7 resume. Thanks to Joseph Lo <josephl@nvidia.com> for bug fixes. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> |
||
|---|---|---|
| .. | ||
| clk-audio-sync.c | ||
| clk-bpmp.c | ||
| clk-dfll.c | ||
| clk-dfll.h | ||
| clk-divider.c | ||
| clk-emc.c | ||
| clk-id.h | ||
| clk-periph-fixed.c | ||
| clk-periph-gate.c | ||
| clk-periph.c | ||
| clk-pll-out.c | ||
| clk-pll.c | ||
| clk-super.c | ||
| clk-tegra20.c | ||
| clk-tegra30.c | ||
| clk-tegra114.c | ||
| clk-tegra124-dfll-fcpu.c | ||
| clk-tegra124.c | ||
| clk-tegra210.c | ||
| clk-tegra-audio.c | ||
| clk-tegra-fixed.c | ||
| clk-tegra-periph.c | ||
| clk-tegra-pmc.c | ||
| clk-tegra-super-gen4.c | ||
| clk.c | ||
| clk.h | ||
| cvb.c | ||
| cvb.h | ||
| Kconfig | ||
| Makefile | ||