forked from Minki/linux
bc860c2071
The mmc_host_ops structure is only stored in the ops field of an mmc_host structure, which is declared as const. Thus the mmc_host_ops structure itself can be const. Done with the help of Coccinelle. // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct mmc_host_ops i@p = { ... }; @ok1@ struct mmc_host *mmc; identifier r.i; position p; @@ mmc->ops = &i@p @bad@ position p != {r.p,ok1.p}; identifier r.i; struct mmc_host_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct mmc_host_ops i = { ... }; // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
729 lines
17 KiB
C
729 lines
17 KiB
C
/*
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* MOXA ART MMC host driver.
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*
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* Copyright (C) 2014 Jonas Jensen
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*
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* Jonas Jensen <jonas.jensen@gmail.com>
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*
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* Based on code from
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* Moxa Technologies Co., Ltd. <www.moxa.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/blkdev.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/sd.h>
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#include <linux/sched.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/clk.h>
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#include <linux/bitops.h>
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#include <linux/of_dma.h>
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#include <linux/spinlock.h>
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#define REG_COMMAND 0
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#define REG_ARGUMENT 4
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#define REG_RESPONSE0 8
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#define REG_RESPONSE1 12
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#define REG_RESPONSE2 16
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#define REG_RESPONSE3 20
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#define REG_RESPONSE_COMMAND 24
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#define REG_DATA_CONTROL 28
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#define REG_DATA_TIMER 32
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#define REG_DATA_LENGTH 36
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#define REG_STATUS 40
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#define REG_CLEAR 44
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#define REG_INTERRUPT_MASK 48
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#define REG_POWER_CONTROL 52
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#define REG_CLOCK_CONTROL 56
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#define REG_BUS_WIDTH 60
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#define REG_DATA_WINDOW 64
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#define REG_FEATURE 68
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#define REG_REVISION 72
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/* REG_COMMAND */
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#define CMD_SDC_RESET BIT(10)
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#define CMD_EN BIT(9)
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#define CMD_APP_CMD BIT(8)
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#define CMD_LONG_RSP BIT(7)
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#define CMD_NEED_RSP BIT(6)
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#define CMD_IDX_MASK 0x3f
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/* REG_RESPONSE_COMMAND */
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#define RSP_CMD_APP BIT(6)
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#define RSP_CMD_IDX_MASK 0x3f
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/* REG_DATA_CONTROL */
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#define DCR_DATA_FIFO_RESET BIT(8)
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#define DCR_DATA_THRES BIT(7)
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#define DCR_DATA_EN BIT(6)
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#define DCR_DMA_EN BIT(5)
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#define DCR_DATA_WRITE BIT(4)
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#define DCR_BLK_SIZE 0x0f
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/* REG_DATA_LENGTH */
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#define DATA_LEN_MASK 0xffffff
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/* REG_STATUS */
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#define WRITE_PROT BIT(12)
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#define CARD_DETECT BIT(11)
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/* 1-10 below can be sent to either registers, interrupt or clear. */
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#define CARD_CHANGE BIT(10)
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#define FIFO_ORUN BIT(9)
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#define FIFO_URUN BIT(8)
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#define DATA_END BIT(7)
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#define CMD_SENT BIT(6)
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#define DATA_CRC_OK BIT(5)
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#define RSP_CRC_OK BIT(4)
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#define DATA_TIMEOUT BIT(3)
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#define RSP_TIMEOUT BIT(2)
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#define DATA_CRC_FAIL BIT(1)
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#define RSP_CRC_FAIL BIT(0)
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#define MASK_RSP (RSP_TIMEOUT | RSP_CRC_FAIL | \
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RSP_CRC_OK | CARD_DETECT | CMD_SENT)
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#define MASK_DATA (DATA_CRC_OK | DATA_END | \
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DATA_CRC_FAIL | DATA_TIMEOUT)
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#define MASK_INTR_PIO (FIFO_URUN | FIFO_ORUN | CARD_CHANGE)
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/* REG_POWER_CONTROL */
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#define SD_POWER_ON BIT(4)
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#define SD_POWER_MASK 0x0f
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/* REG_CLOCK_CONTROL */
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#define CLK_HISPD BIT(9)
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#define CLK_OFF BIT(8)
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#define CLK_SD BIT(7)
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#define CLK_DIV_MASK 0x7f
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/* REG_BUS_WIDTH */
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#define BUS_WIDTH_8 BIT(2)
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#define BUS_WIDTH_4 BIT(1)
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#define BUS_WIDTH_1 BIT(0)
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#define MMC_VDD_360 23
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#define MIN_POWER (MMC_VDD_360 - SD_POWER_MASK)
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#define MAX_RETRIES 500000
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struct moxart_host {
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spinlock_t lock;
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void __iomem *base;
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phys_addr_t reg_phys;
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struct dma_chan *dma_chan_tx;
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struct dma_chan *dma_chan_rx;
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struct dma_async_tx_descriptor *tx_desc;
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struct mmc_host *mmc;
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struct mmc_request *mrq;
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struct scatterlist *cur_sg;
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struct completion dma_complete;
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struct completion pio_complete;
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u32 num_sg;
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u32 data_remain;
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u32 data_len;
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u32 fifo_width;
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u32 timeout;
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u32 rate;
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long sysclk;
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bool have_dma;
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bool is_removed;
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};
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static inline void moxart_init_sg(struct moxart_host *host,
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struct mmc_data *data)
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{
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host->cur_sg = data->sg;
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host->num_sg = data->sg_len;
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host->data_remain = host->cur_sg->length;
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if (host->data_remain > host->data_len)
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host->data_remain = host->data_len;
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}
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static inline int moxart_next_sg(struct moxart_host *host)
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{
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int remain;
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struct mmc_data *data = host->mrq->cmd->data;
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host->cur_sg++;
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host->num_sg--;
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if (host->num_sg > 0) {
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host->data_remain = host->cur_sg->length;
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remain = host->data_len - data->bytes_xfered;
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if (remain > 0 && remain < host->data_remain)
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host->data_remain = remain;
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}
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return host->num_sg;
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}
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static int moxart_wait_for_status(struct moxart_host *host,
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u32 mask, u32 *status)
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{
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int ret = -ETIMEDOUT;
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u32 i;
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for (i = 0; i < MAX_RETRIES; i++) {
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*status = readl(host->base + REG_STATUS);
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if (!(*status & mask)) {
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udelay(5);
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continue;
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}
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writel(*status & mask, host->base + REG_CLEAR);
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ret = 0;
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break;
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}
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if (ret)
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dev_err(mmc_dev(host->mmc), "timed out waiting for status\n");
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return ret;
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}
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static void moxart_send_command(struct moxart_host *host,
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struct mmc_command *cmd)
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{
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u32 status, cmdctrl;
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writel(RSP_TIMEOUT | RSP_CRC_OK |
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RSP_CRC_FAIL | CMD_SENT, host->base + REG_CLEAR);
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writel(cmd->arg, host->base + REG_ARGUMENT);
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cmdctrl = cmd->opcode & CMD_IDX_MASK;
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if (cmdctrl == SD_APP_SET_BUS_WIDTH || cmdctrl == SD_APP_OP_COND ||
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cmdctrl == SD_APP_SEND_SCR || cmdctrl == SD_APP_SD_STATUS ||
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cmdctrl == SD_APP_SEND_NUM_WR_BLKS)
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cmdctrl |= CMD_APP_CMD;
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if (cmd->flags & MMC_RSP_PRESENT)
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cmdctrl |= CMD_NEED_RSP;
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if (cmd->flags & MMC_RSP_136)
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cmdctrl |= CMD_LONG_RSP;
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writel(cmdctrl | CMD_EN, host->base + REG_COMMAND);
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if (moxart_wait_for_status(host, MASK_RSP, &status) == -ETIMEDOUT)
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cmd->error = -ETIMEDOUT;
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if (status & RSP_TIMEOUT) {
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cmd->error = -ETIMEDOUT;
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return;
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}
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if (status & RSP_CRC_FAIL) {
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cmd->error = -EIO;
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return;
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}
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if (status & RSP_CRC_OK) {
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if (cmd->flags & MMC_RSP_136) {
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cmd->resp[3] = readl(host->base + REG_RESPONSE0);
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cmd->resp[2] = readl(host->base + REG_RESPONSE1);
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cmd->resp[1] = readl(host->base + REG_RESPONSE2);
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cmd->resp[0] = readl(host->base + REG_RESPONSE3);
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} else {
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cmd->resp[0] = readl(host->base + REG_RESPONSE0);
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}
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}
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}
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static void moxart_dma_complete(void *param)
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{
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struct moxart_host *host = param;
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complete(&host->dma_complete);
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}
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static void moxart_transfer_dma(struct mmc_data *data, struct moxart_host *host)
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{
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u32 len, dir_slave;
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long dma_time;
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struct dma_async_tx_descriptor *desc = NULL;
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struct dma_chan *dma_chan;
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if (host->data_len == data->bytes_xfered)
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return;
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if (data->flags & MMC_DATA_WRITE) {
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dma_chan = host->dma_chan_tx;
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dir_slave = DMA_MEM_TO_DEV;
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} else {
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dma_chan = host->dma_chan_rx;
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dir_slave = DMA_DEV_TO_MEM;
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}
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len = dma_map_sg(dma_chan->device->dev, data->sg,
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data->sg_len, mmc_get_dma_dir(data));
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if (len > 0) {
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desc = dmaengine_prep_slave_sg(dma_chan, data->sg,
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len, dir_slave,
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DMA_PREP_INTERRUPT |
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DMA_CTRL_ACK);
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} else {
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dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n");
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}
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if (desc) {
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host->tx_desc = desc;
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desc->callback = moxart_dma_complete;
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desc->callback_param = host;
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dmaengine_submit(desc);
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dma_async_issue_pending(dma_chan);
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}
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data->bytes_xfered += host->data_remain;
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dma_time = wait_for_completion_interruptible_timeout(
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&host->dma_complete, host->timeout);
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dma_unmap_sg(dma_chan->device->dev,
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data->sg, data->sg_len,
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mmc_get_dma_dir(data));
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}
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static void moxart_transfer_pio(struct moxart_host *host)
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{
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struct mmc_data *data = host->mrq->cmd->data;
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u32 *sgp, len = 0, remain, status;
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if (host->data_len == data->bytes_xfered)
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return;
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sgp = sg_virt(host->cur_sg);
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remain = host->data_remain;
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if (data->flags & MMC_DATA_WRITE) {
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while (remain > 0) {
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if (moxart_wait_for_status(host, FIFO_URUN, &status)
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== -ETIMEDOUT) {
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data->error = -ETIMEDOUT;
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complete(&host->pio_complete);
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return;
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}
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for (len = 0; len < remain && len < host->fifo_width;) {
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iowrite32(*sgp, host->base + REG_DATA_WINDOW);
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sgp++;
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len += 4;
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}
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remain -= len;
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}
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} else {
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while (remain > 0) {
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if (moxart_wait_for_status(host, FIFO_ORUN, &status)
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== -ETIMEDOUT) {
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data->error = -ETIMEDOUT;
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complete(&host->pio_complete);
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return;
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}
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for (len = 0; len < remain && len < host->fifo_width;) {
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/* SCR data must be read in big endian. */
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if (data->mrq->cmd->opcode == SD_APP_SEND_SCR)
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*sgp = ioread32be(host->base +
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REG_DATA_WINDOW);
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else
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*sgp = ioread32(host->base +
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REG_DATA_WINDOW);
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sgp++;
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len += 4;
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}
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remain -= len;
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}
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}
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data->bytes_xfered += host->data_remain - remain;
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host->data_remain = remain;
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if (host->data_len != data->bytes_xfered)
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moxart_next_sg(host);
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else
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complete(&host->pio_complete);
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}
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static void moxart_prepare_data(struct moxart_host *host)
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{
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struct mmc_data *data = host->mrq->cmd->data;
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u32 datactrl;
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int blksz_bits;
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if (!data)
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return;
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host->data_len = data->blocks * data->blksz;
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blksz_bits = ffs(data->blksz) - 1;
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BUG_ON(1 << blksz_bits != data->blksz);
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moxart_init_sg(host, data);
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datactrl = DCR_DATA_EN | (blksz_bits & DCR_BLK_SIZE);
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if (data->flags & MMC_DATA_WRITE)
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datactrl |= DCR_DATA_WRITE;
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if ((host->data_len > host->fifo_width) && host->have_dma)
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datactrl |= DCR_DMA_EN;
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writel(DCR_DATA_FIFO_RESET, host->base + REG_DATA_CONTROL);
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writel(MASK_DATA | FIFO_URUN | FIFO_ORUN, host->base + REG_CLEAR);
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writel(host->rate, host->base + REG_DATA_TIMER);
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writel(host->data_len, host->base + REG_DATA_LENGTH);
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writel(datactrl, host->base + REG_DATA_CONTROL);
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}
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static void moxart_request(struct mmc_host *mmc, struct mmc_request *mrq)
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{
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struct moxart_host *host = mmc_priv(mmc);
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long pio_time;
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unsigned long flags;
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u32 status;
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spin_lock_irqsave(&host->lock, flags);
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init_completion(&host->dma_complete);
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init_completion(&host->pio_complete);
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host->mrq = mrq;
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if (readl(host->base + REG_STATUS) & CARD_DETECT) {
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mrq->cmd->error = -ETIMEDOUT;
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goto request_done;
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}
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moxart_prepare_data(host);
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moxart_send_command(host, host->mrq->cmd);
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if (mrq->cmd->data) {
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if ((host->data_len > host->fifo_width) && host->have_dma) {
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writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK);
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spin_unlock_irqrestore(&host->lock, flags);
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moxart_transfer_dma(mrq->cmd->data, host);
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spin_lock_irqsave(&host->lock, flags);
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} else {
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writel(MASK_INTR_PIO, host->base + REG_INTERRUPT_MASK);
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spin_unlock_irqrestore(&host->lock, flags);
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/* PIO transfers start from interrupt. */
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pio_time = wait_for_completion_interruptible_timeout(
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&host->pio_complete, host->timeout);
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spin_lock_irqsave(&host->lock, flags);
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}
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if (host->is_removed) {
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dev_err(mmc_dev(host->mmc), "card removed\n");
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mrq->cmd->error = -ETIMEDOUT;
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goto request_done;
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}
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if (moxart_wait_for_status(host, MASK_DATA, &status)
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== -ETIMEDOUT) {
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mrq->cmd->data->error = -ETIMEDOUT;
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goto request_done;
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}
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if (status & DATA_CRC_FAIL)
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mrq->cmd->data->error = -ETIMEDOUT;
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if (mrq->cmd->data->stop)
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moxart_send_command(host, mrq->cmd->data->stop);
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}
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request_done:
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spin_unlock_irqrestore(&host->lock, flags);
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mmc_request_done(host->mmc, mrq);
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}
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static irqreturn_t moxart_irq(int irq, void *devid)
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{
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struct moxart_host *host = (struct moxart_host *)devid;
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u32 status;
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unsigned long flags;
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spin_lock_irqsave(&host->lock, flags);
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status = readl(host->base + REG_STATUS);
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if (status & CARD_CHANGE) {
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host->is_removed = status & CARD_DETECT;
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if (host->is_removed && host->have_dma) {
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dmaengine_terminate_all(host->dma_chan_tx);
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dmaengine_terminate_all(host->dma_chan_rx);
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}
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host->mrq = NULL;
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writel(MASK_INTR_PIO, host->base + REG_CLEAR);
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writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK);
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mmc_detect_change(host->mmc, 0);
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}
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if (status & (FIFO_ORUN | FIFO_URUN) && host->mrq)
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moxart_transfer_pio(host);
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spin_unlock_irqrestore(&host->lock, flags);
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return IRQ_HANDLED;
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}
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static void moxart_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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{
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struct moxart_host *host = mmc_priv(mmc);
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unsigned long flags;
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u8 power, div;
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u32 ctrl;
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
if (ios->clock) {
|
|
for (div = 0; div < CLK_DIV_MASK; ++div) {
|
|
if (ios->clock >= host->sysclk / (2 * (div + 1)))
|
|
break;
|
|
}
|
|
ctrl = CLK_SD | div;
|
|
host->rate = host->sysclk / (2 * (div + 1));
|
|
if (host->rate > host->sysclk)
|
|
ctrl |= CLK_HISPD;
|
|
writel(ctrl, host->base + REG_CLOCK_CONTROL);
|
|
}
|
|
|
|
if (ios->power_mode == MMC_POWER_OFF) {
|
|
writel(readl(host->base + REG_POWER_CONTROL) & ~SD_POWER_ON,
|
|
host->base + REG_POWER_CONTROL);
|
|
} else {
|
|
if (ios->vdd < MIN_POWER)
|
|
power = 0;
|
|
else
|
|
power = ios->vdd - MIN_POWER;
|
|
|
|
writel(SD_POWER_ON | (u32) power,
|
|
host->base + REG_POWER_CONTROL);
|
|
}
|
|
|
|
switch (ios->bus_width) {
|
|
case MMC_BUS_WIDTH_4:
|
|
writel(BUS_WIDTH_4, host->base + REG_BUS_WIDTH);
|
|
break;
|
|
case MMC_BUS_WIDTH_8:
|
|
writel(BUS_WIDTH_8, host->base + REG_BUS_WIDTH);
|
|
break;
|
|
default:
|
|
writel(BUS_WIDTH_1, host->base + REG_BUS_WIDTH);
|
|
break;
|
|
}
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
}
|
|
|
|
|
|
static int moxart_get_ro(struct mmc_host *mmc)
|
|
{
|
|
struct moxart_host *host = mmc_priv(mmc);
|
|
|
|
return !!(readl(host->base + REG_STATUS) & WRITE_PROT);
|
|
}
|
|
|
|
static const struct mmc_host_ops moxart_ops = {
|
|
.request = moxart_request,
|
|
.set_ios = moxart_set_ios,
|
|
.get_ro = moxart_get_ro,
|
|
};
|
|
|
|
static int moxart_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *node = dev->of_node;
|
|
struct resource res_mmc;
|
|
struct mmc_host *mmc;
|
|
struct moxart_host *host = NULL;
|
|
struct dma_slave_config cfg;
|
|
struct clk *clk;
|
|
void __iomem *reg_mmc;
|
|
int irq, ret;
|
|
u32 i;
|
|
|
|
mmc = mmc_alloc_host(sizeof(struct moxart_host), dev);
|
|
if (!mmc) {
|
|
dev_err(dev, "mmc_alloc_host failed\n");
|
|
ret = -ENOMEM;
|
|
goto out;
|
|
}
|
|
|
|
ret = of_address_to_resource(node, 0, &res_mmc);
|
|
if (ret) {
|
|
dev_err(dev, "of_address_to_resource failed\n");
|
|
goto out;
|
|
}
|
|
|
|
irq = irq_of_parse_and_map(node, 0);
|
|
if (irq <= 0) {
|
|
dev_err(dev, "irq_of_parse_and_map failed\n");
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
clk = devm_clk_get(dev, NULL);
|
|
if (IS_ERR(clk)) {
|
|
ret = PTR_ERR(clk);
|
|
goto out;
|
|
}
|
|
|
|
reg_mmc = devm_ioremap_resource(dev, &res_mmc);
|
|
if (IS_ERR(reg_mmc)) {
|
|
ret = PTR_ERR(reg_mmc);
|
|
goto out;
|
|
}
|
|
|
|
ret = mmc_of_parse(mmc);
|
|
if (ret)
|
|
goto out;
|
|
|
|
host = mmc_priv(mmc);
|
|
host->mmc = mmc;
|
|
host->base = reg_mmc;
|
|
host->reg_phys = res_mmc.start;
|
|
host->timeout = msecs_to_jiffies(1000);
|
|
host->sysclk = clk_get_rate(clk);
|
|
host->fifo_width = readl(host->base + REG_FEATURE) << 2;
|
|
host->dma_chan_tx = dma_request_slave_channel_reason(dev, "tx");
|
|
host->dma_chan_rx = dma_request_slave_channel_reason(dev, "rx");
|
|
|
|
spin_lock_init(&host->lock);
|
|
|
|
mmc->ops = &moxart_ops;
|
|
mmc->f_max = DIV_ROUND_CLOSEST(host->sysclk, 2);
|
|
mmc->f_min = DIV_ROUND_CLOSEST(host->sysclk, CLK_DIV_MASK * 2);
|
|
mmc->ocr_avail = 0xffff00; /* Support 2.0v - 3.6v power. */
|
|
|
|
if (IS_ERR(host->dma_chan_tx) || IS_ERR(host->dma_chan_rx)) {
|
|
if (PTR_ERR(host->dma_chan_tx) == -EPROBE_DEFER ||
|
|
PTR_ERR(host->dma_chan_rx) == -EPROBE_DEFER) {
|
|
ret = -EPROBE_DEFER;
|
|
goto out;
|
|
}
|
|
dev_dbg(dev, "PIO mode transfer enabled\n");
|
|
host->have_dma = false;
|
|
} else {
|
|
dev_dbg(dev, "DMA channels found (%p,%p)\n",
|
|
host->dma_chan_tx, host->dma_chan_rx);
|
|
host->have_dma = true;
|
|
|
|
cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
|
|
cfg.direction = DMA_MEM_TO_DEV;
|
|
cfg.src_addr = 0;
|
|
cfg.dst_addr = host->reg_phys + REG_DATA_WINDOW;
|
|
dmaengine_slave_config(host->dma_chan_tx, &cfg);
|
|
|
|
cfg.direction = DMA_DEV_TO_MEM;
|
|
cfg.src_addr = host->reg_phys + REG_DATA_WINDOW;
|
|
cfg.dst_addr = 0;
|
|
dmaengine_slave_config(host->dma_chan_rx, &cfg);
|
|
}
|
|
|
|
switch ((readl(host->base + REG_BUS_WIDTH) >> 3) & 3) {
|
|
case 1:
|
|
mmc->caps |= MMC_CAP_4_BIT_DATA;
|
|
break;
|
|
case 2:
|
|
mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
writel(0, host->base + REG_INTERRUPT_MASK);
|
|
|
|
writel(CMD_SDC_RESET, host->base + REG_COMMAND);
|
|
for (i = 0; i < MAX_RETRIES; i++) {
|
|
if (!(readl(host->base + REG_COMMAND) & CMD_SDC_RESET))
|
|
break;
|
|
udelay(5);
|
|
}
|
|
|
|
ret = devm_request_irq(dev, irq, moxart_irq, 0, "moxart-mmc", host);
|
|
if (ret)
|
|
goto out;
|
|
|
|
dev_set_drvdata(dev, mmc);
|
|
mmc_add_host(mmc);
|
|
|
|
dev_dbg(dev, "IRQ=%d, FIFO is %d bytes\n", irq, host->fifo_width);
|
|
|
|
return 0;
|
|
|
|
out:
|
|
if (mmc)
|
|
mmc_free_host(mmc);
|
|
return ret;
|
|
}
|
|
|
|
static int moxart_remove(struct platform_device *pdev)
|
|
{
|
|
struct mmc_host *mmc = dev_get_drvdata(&pdev->dev);
|
|
struct moxart_host *host = mmc_priv(mmc);
|
|
|
|
dev_set_drvdata(&pdev->dev, NULL);
|
|
|
|
if (mmc) {
|
|
if (!IS_ERR(host->dma_chan_tx))
|
|
dma_release_channel(host->dma_chan_tx);
|
|
if (!IS_ERR(host->dma_chan_rx))
|
|
dma_release_channel(host->dma_chan_rx);
|
|
mmc_remove_host(mmc);
|
|
mmc_free_host(mmc);
|
|
|
|
writel(0, host->base + REG_INTERRUPT_MASK);
|
|
writel(0, host->base + REG_POWER_CONTROL);
|
|
writel(readl(host->base + REG_CLOCK_CONTROL) | CLK_OFF,
|
|
host->base + REG_CLOCK_CONTROL);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id moxart_mmc_match[] = {
|
|
{ .compatible = "moxa,moxart-mmc" },
|
|
{ .compatible = "faraday,ftsdc010" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, moxart_mmc_match);
|
|
|
|
static struct platform_driver moxart_mmc_driver = {
|
|
.probe = moxart_probe,
|
|
.remove = moxart_remove,
|
|
.driver = {
|
|
.name = "mmc-moxart",
|
|
.of_match_table = moxart_mmc_match,
|
|
},
|
|
};
|
|
module_platform_driver(moxart_mmc_driver);
|
|
|
|
MODULE_ALIAS("platform:mmc-moxart");
|
|
MODULE_DESCRIPTION("MOXA ART MMC driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");
|