forked from Minki/linux
2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
397 lines
11 KiB
C
397 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/mmc/host.h>
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#include <linux/of_address.h>
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#include <linux/mmc/slot-gpio.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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#define RK3288_CLKGEN_DIV 2
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struct dw_mci_rockchip_priv_data {
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struct clk *drv_clk;
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struct clk *sample_clk;
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int default_sample_phase;
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int num_phases;
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};
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static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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{
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struct dw_mci_rockchip_priv_data *priv = host->priv;
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int ret;
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unsigned int cclkin;
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u32 bus_hz;
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if (ios->clock == 0)
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return;
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/*
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* cclkin: source clock of mmc controller
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* bus_hz: card interface clock generated by CLKGEN
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* bus_hz = cclkin / RK3288_CLKGEN_DIV
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* ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))
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*
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* Note: div can only be 0 or 1, but div must be set to 1 for eMMC
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* DDR52 8-bit mode.
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*/
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if (ios->bus_width == MMC_BUS_WIDTH_8 &&
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ios->timing == MMC_TIMING_MMC_DDR52)
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cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;
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else
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cclkin = ios->clock * RK3288_CLKGEN_DIV;
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ret = clk_set_rate(host->ciu_clk, cclkin);
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if (ret)
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dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
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bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
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if (bus_hz != host->bus_hz) {
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host->bus_hz = bus_hz;
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/* force dw_mci_setup_bus() */
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host->current_speed = 0;
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}
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/* Make sure we use phases which we can enumerate with */
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if (!IS_ERR(priv->sample_clk))
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clk_set_phase(priv->sample_clk, priv->default_sample_phase);
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/*
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* Set the drive phase offset based on speed mode to achieve hold times.
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*
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* NOTE: this is _not_ a value that is dynamically tuned and is also
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* _not_ a value that will vary from board to board. It is a value
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* that could vary between different SoC models if they had massively
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* different output clock delays inside their dw_mmc IP block (delay_o),
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* but since it's OK to overshoot a little we don't need to do complex
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* calculations and can pick values that will just work for everyone.
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*
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* When picking values we'll stick with picking 0/90/180/270 since
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* those can be made very accurately on all known Rockchip SoCs.
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*
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* Note that these values match values from the DesignWare Databook
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* tables for the most part except for SDR12 and "ID mode". For those
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* two modes the databook calculations assume a clock in of 50MHz. As
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* seen above, we always use a clock in rate that is exactly the
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* card's input clock (times RK3288_CLKGEN_DIV, but that gets divided
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* back out before the controller sees it).
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*
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* From measurement of a single device, it appears that delay_o is
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* about .5 ns. Since we try to leave a bit of margin, it's expected
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* that numbers here will be fine even with much larger delay_o
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* (the 1.4 ns assumed by the DesignWare Databook would result in the
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* same results, for instance).
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*/
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if (!IS_ERR(priv->drv_clk)) {
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int phase;
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/*
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* In almost all cases a 90 degree phase offset will provide
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* sufficient hold times across all valid input clock rates
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* assuming delay_o is not absurd for a given SoC. We'll use
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* that as a default.
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*/
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phase = 90;
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switch (ios->timing) {
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case MMC_TIMING_MMC_DDR52:
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/*
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* Since clock in rate with MMC_DDR52 is doubled when
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* bus width is 8 we need to double the phase offset
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* to get the same timings.
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*/
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if (ios->bus_width == MMC_BUS_WIDTH_8)
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phase = 180;
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break;
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case MMC_TIMING_UHS_SDR104:
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case MMC_TIMING_MMC_HS200:
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/*
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* In the case of 150 MHz clock (typical max for
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* Rockchip SoCs), 90 degree offset will add a delay
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* of 1.67 ns. That will meet min hold time of .8 ns
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* as long as clock output delay is < .87 ns. On
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* SoCs measured this seems to be OK, but it doesn't
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* hurt to give margin here, so we use 180.
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*/
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phase = 180;
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break;
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}
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clk_set_phase(priv->drv_clk, phase);
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}
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}
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#define TUNING_ITERATION_TO_PHASE(i, num_phases) \
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(DIV_ROUND_UP((i) * 360, num_phases))
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static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
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{
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struct dw_mci *host = slot->host;
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struct dw_mci_rockchip_priv_data *priv = host->priv;
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struct mmc_host *mmc = slot->mmc;
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int ret = 0;
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int i;
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bool v, prev_v = 0, first_v;
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struct range_t {
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int start;
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int end; /* inclusive */
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};
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struct range_t *ranges;
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unsigned int range_count = 0;
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int longest_range_len = -1;
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int longest_range = -1;
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int middle_phase;
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if (IS_ERR(priv->sample_clk)) {
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dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n");
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return -EIO;
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}
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ranges = kmalloc_array(priv->num_phases / 2 + 1,
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sizeof(*ranges), GFP_KERNEL);
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if (!ranges)
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return -ENOMEM;
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/* Try each phase and extract good ranges */
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for (i = 0; i < priv->num_phases; ) {
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clk_set_phase(priv->sample_clk,
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TUNING_ITERATION_TO_PHASE(i, priv->num_phases));
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v = !mmc_send_tuning(mmc, opcode, NULL);
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if (i == 0)
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first_v = v;
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if ((!prev_v) && v) {
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range_count++;
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ranges[range_count-1].start = i;
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}
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if (v) {
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ranges[range_count-1].end = i;
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i++;
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} else if (i == priv->num_phases - 1) {
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/* No extra skipping rules if we're at the end */
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i++;
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} else {
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/*
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* No need to check too close to an invalid
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* one since testing bad phases is slow. Skip
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* 20 degrees.
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*/
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i += DIV_ROUND_UP(20 * priv->num_phases, 360);
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/* Always test the last one */
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if (i >= priv->num_phases)
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i = priv->num_phases - 1;
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}
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prev_v = v;
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}
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if (range_count == 0) {
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dev_warn(host->dev, "All phases bad!");
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ret = -EIO;
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goto free;
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}
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/* wrap around case, merge the end points */
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if ((range_count > 1) && first_v && v) {
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ranges[0].start = ranges[range_count-1].start;
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range_count--;
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}
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if (ranges[0].start == 0 && ranges[0].end == priv->num_phases - 1) {
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clk_set_phase(priv->sample_clk, priv->default_sample_phase);
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dev_info(host->dev, "All phases work, using default phase %d.",
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priv->default_sample_phase);
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goto free;
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}
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/* Find the longest range */
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for (i = 0; i < range_count; i++) {
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int len = (ranges[i].end - ranges[i].start + 1);
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if (len < 0)
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len += priv->num_phases;
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if (longest_range_len < len) {
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longest_range_len = len;
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longest_range = i;
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}
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dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n",
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TUNING_ITERATION_TO_PHASE(ranges[i].start,
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priv->num_phases),
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TUNING_ITERATION_TO_PHASE(ranges[i].end,
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priv->num_phases),
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len
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);
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}
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dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n",
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TUNING_ITERATION_TO_PHASE(ranges[longest_range].start,
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priv->num_phases),
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TUNING_ITERATION_TO_PHASE(ranges[longest_range].end,
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priv->num_phases),
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longest_range_len
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);
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middle_phase = ranges[longest_range].start + longest_range_len / 2;
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middle_phase %= priv->num_phases;
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dev_info(host->dev, "Successfully tuned phase to %d\n",
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TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases));
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clk_set_phase(priv->sample_clk,
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TUNING_ITERATION_TO_PHASE(middle_phase,
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priv->num_phases));
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free:
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kfree(ranges);
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return ret;
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}
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static int dw_mci_rk3288_parse_dt(struct dw_mci *host)
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{
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struct device_node *np = host->dev->of_node;
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struct dw_mci_rockchip_priv_data *priv;
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priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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if (of_property_read_u32(np, "rockchip,desired-num-phases",
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&priv->num_phases))
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priv->num_phases = 360;
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if (of_property_read_u32(np, "rockchip,default-sample-phase",
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&priv->default_sample_phase))
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priv->default_sample_phase = 0;
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priv->drv_clk = devm_clk_get(host->dev, "ciu-drive");
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if (IS_ERR(priv->drv_clk))
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dev_dbg(host->dev, "ciu-drive not available\n");
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priv->sample_clk = devm_clk_get(host->dev, "ciu-sample");
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if (IS_ERR(priv->sample_clk))
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dev_dbg(host->dev, "ciu-sample not available\n");
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host->priv = priv;
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return 0;
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}
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static int dw_mci_rockchip_init(struct dw_mci *host)
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{
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/* It is slot 8 on Rockchip SoCs */
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host->sdio_id0 = 8;
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if (of_device_is_compatible(host->dev->of_node,
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"rockchip,rk3288-dw-mshc"))
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host->bus_hz /= RK3288_CLKGEN_DIV;
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return 0;
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}
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/* Common capabilities of RK3288 SoC */
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static unsigned long dw_mci_rk3288_dwmmc_caps[4] = {
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MMC_CAP_CMD23,
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MMC_CAP_CMD23,
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MMC_CAP_CMD23,
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MMC_CAP_CMD23,
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};
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static const struct dw_mci_drv_data rk2928_drv_data = {
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.init = dw_mci_rockchip_init,
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};
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static const struct dw_mci_drv_data rk3288_drv_data = {
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.caps = dw_mci_rk3288_dwmmc_caps,
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.num_caps = ARRAY_SIZE(dw_mci_rk3288_dwmmc_caps),
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.set_ios = dw_mci_rk3288_set_ios,
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.execute_tuning = dw_mci_rk3288_execute_tuning,
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.parse_dt = dw_mci_rk3288_parse_dt,
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.init = dw_mci_rockchip_init,
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};
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static const struct of_device_id dw_mci_rockchip_match[] = {
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{ .compatible = "rockchip,rk2928-dw-mshc",
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.data = &rk2928_drv_data },
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{ .compatible = "rockchip,rk3288-dw-mshc",
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.data = &rk3288_drv_data },
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{},
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};
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MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
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static int dw_mci_rockchip_probe(struct platform_device *pdev)
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{
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const struct dw_mci_drv_data *drv_data;
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const struct of_device_id *match;
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int ret;
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if (!pdev->dev.of_node)
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return -ENODEV;
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match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
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drv_data = match->data;
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pm_runtime_get_noresume(&pdev->dev);
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
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pm_runtime_use_autosuspend(&pdev->dev);
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ret = dw_mci_pltfm_register(pdev, drv_data);
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if (ret) {
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pm_runtime_disable(&pdev->dev);
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pm_runtime_set_suspended(&pdev->dev);
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pm_runtime_put_noidle(&pdev->dev);
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return ret;
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}
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pm_runtime_put_autosuspend(&pdev->dev);
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return 0;
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}
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static int dw_mci_rockchip_remove(struct platform_device *pdev)
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{
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pm_runtime_get_sync(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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pm_runtime_put_noidle(&pdev->dev);
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return dw_mci_pltfm_remove(pdev);
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}
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static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
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dw_mci_runtime_resume,
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NULL)
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};
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static struct platform_driver dw_mci_rockchip_pltfm_driver = {
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.probe = dw_mci_rockchip_probe,
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.remove = dw_mci_rockchip_remove,
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.driver = {
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.name = "dwmmc_rockchip",
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.of_match_table = dw_mci_rockchip_match,
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.pm = &dw_mci_rockchip_dev_pm_ops,
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},
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};
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module_platform_driver(dw_mci_rockchip_pltfm_driver);
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MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
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MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");
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MODULE_ALIAS("platform:dwmmc_rockchip");
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MODULE_LICENSE("GPL v2");
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