forked from Minki/linux
4fbafaf371
Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
373 lines
7.9 KiB
C
373 lines
7.9 KiB
C
/*
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* linux/drivers/video/omap2/dss/dpi.c
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*
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* Copyright (C) 2009 Nokia Corporation
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* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
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*
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* Some code and ideas taken from drivers/video/omap/ driver
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* by Imre Deak.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define DSS_SUBSYS_NAME "DPI"
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <video/omapdss.h>
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#include <plat/cpu.h>
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#include "dss.h"
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static struct {
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struct regulator *vdds_dsi_reg;
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struct platform_device *dsidev;
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} dpi;
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static struct platform_device *dpi_get_dsidev(enum omap_dss_clk_source clk)
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{
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int dsi_module;
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dsi_module = clk == OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ? 0 : 1;
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return dsi_get_dsidev_from_id(dsi_module);
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}
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static bool dpi_use_dsi_pll(struct omap_dss_device *dssdev)
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{
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if (dssdev->clocks.dispc.dispc_fclk_src ==
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OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
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dssdev->clocks.dispc.dispc_fclk_src ==
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OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC ||
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dssdev->clocks.dispc.channel.lcd_clk_src ==
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OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
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dssdev->clocks.dispc.channel.lcd_clk_src ==
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OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC)
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return true;
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else
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return false;
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}
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static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
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unsigned long pck_req, unsigned long *fck, int *lck_div,
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int *pck_div)
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{
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struct dsi_clock_info dsi_cinfo;
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struct dispc_clock_info dispc_cinfo;
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int r;
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r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft, pck_req,
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&dsi_cinfo, &dispc_cinfo);
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if (r)
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return r;
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r = dsi_pll_set_clock_div(dpi.dsidev, &dsi_cinfo);
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if (r)
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return r;
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dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
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r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
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if (r)
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return r;
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*fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
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*lck_div = dispc_cinfo.lck_div;
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*pck_div = dispc_cinfo.pck_div;
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return 0;
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}
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static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft,
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unsigned long pck_req, unsigned long *fck, int *lck_div,
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int *pck_div)
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{
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struct dss_clock_info dss_cinfo;
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struct dispc_clock_info dispc_cinfo;
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int r;
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r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo);
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if (r)
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return r;
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r = dss_set_clock_div(&dss_cinfo);
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if (r)
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return r;
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r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
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if (r)
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return r;
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*fck = dss_cinfo.fck;
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*lck_div = dispc_cinfo.lck_div;
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*pck_div = dispc_cinfo.pck_div;
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return 0;
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}
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static int dpi_set_mode(struct omap_dss_device *dssdev)
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{
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struct omap_video_timings *t = &dssdev->panel.timings;
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int lck_div = 0, pck_div = 0;
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unsigned long fck = 0;
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unsigned long pck;
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bool is_tft;
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int r = 0;
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dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
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dssdev->panel.acbi, dssdev->panel.acb);
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is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
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if (dpi_use_dsi_pll(dssdev))
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r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000,
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&fck, &lck_div, &pck_div);
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else
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r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000,
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&fck, &lck_div, &pck_div);
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if (r)
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return r;
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pck = fck / lck_div / pck_div / 1000;
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if (pck != t->pixel_clock) {
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DSSWARN("Could not find exact pixel clock. "
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"Requested %d kHz, got %lu kHz\n",
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t->pixel_clock, pck);
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t->pixel_clock = pck;
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}
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dispc_set_lcd_timings(dssdev->manager->id, t);
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return 0;
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}
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static void dpi_basic_init(struct omap_dss_device *dssdev)
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{
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bool is_tft;
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is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
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dispc_set_parallel_interface_mode(dssdev->manager->id,
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OMAP_DSS_PARALLELMODE_BYPASS);
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dispc_set_lcd_display_type(dssdev->manager->id, is_tft ?
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OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN);
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dispc_set_tft_data_lines(dssdev->manager->id,
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dssdev->phy.dpi.data_lines);
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}
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int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
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{
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int r;
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r = omap_dss_start_device(dssdev);
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if (r) {
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DSSERR("failed to start device\n");
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goto err_start_dev;
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}
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if (cpu_is_omap34xx()) {
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r = regulator_enable(dpi.vdds_dsi_reg);
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if (r)
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goto err_reg_enable;
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}
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r = dss_runtime_get();
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if (r)
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goto err_get_dss;
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r = dispc_runtime_get();
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if (r)
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goto err_get_dispc;
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dpi_basic_init(dssdev);
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if (dpi_use_dsi_pll(dssdev)) {
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r = dsi_runtime_get(dpi.dsidev);
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if (r)
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goto err_get_dsi;
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r = dsi_pll_init(dpi.dsidev, 0, 1);
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if (r)
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goto err_dsi_pll_init;
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}
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r = dpi_set_mode(dssdev);
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if (r)
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goto err_set_mode;
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mdelay(2);
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dssdev->manager->enable(dssdev->manager);
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return 0;
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err_set_mode:
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if (dpi_use_dsi_pll(dssdev))
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dsi_pll_uninit(dpi.dsidev, true);
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err_dsi_pll_init:
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if (dpi_use_dsi_pll(dssdev))
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dsi_runtime_put(dpi.dsidev);
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err_get_dsi:
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dispc_runtime_put();
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err_get_dispc:
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dss_runtime_put();
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err_get_dss:
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if (cpu_is_omap34xx())
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regulator_disable(dpi.vdds_dsi_reg);
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err_reg_enable:
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omap_dss_stop_device(dssdev);
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err_start_dev:
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return r;
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}
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EXPORT_SYMBOL(omapdss_dpi_display_enable);
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void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
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{
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dssdev->manager->disable(dssdev->manager);
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if (dpi_use_dsi_pll(dssdev)) {
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dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
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dsi_pll_uninit(dpi.dsidev, true);
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dsi_runtime_put(dpi.dsidev);
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}
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dispc_runtime_put();
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dss_runtime_put();
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if (cpu_is_omap34xx())
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regulator_disable(dpi.vdds_dsi_reg);
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omap_dss_stop_device(dssdev);
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}
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EXPORT_SYMBOL(omapdss_dpi_display_disable);
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void dpi_set_timings(struct omap_dss_device *dssdev,
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struct omap_video_timings *timings)
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{
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int r;
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DSSDBG("dpi_set_timings\n");
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dssdev->panel.timings = *timings;
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if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
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r = dss_runtime_get();
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if (r)
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return;
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r = dispc_runtime_get();
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if (r) {
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dss_runtime_put();
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return;
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}
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dpi_set_mode(dssdev);
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dispc_go(dssdev->manager->id);
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dispc_runtime_put();
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dss_runtime_put();
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}
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}
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EXPORT_SYMBOL(dpi_set_timings);
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int dpi_check_timings(struct omap_dss_device *dssdev,
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struct omap_video_timings *timings)
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{
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bool is_tft;
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int r;
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int lck_div, pck_div;
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unsigned long fck;
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unsigned long pck;
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struct dispc_clock_info dispc_cinfo;
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if (!dispc_lcd_timings_ok(timings))
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return -EINVAL;
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if (timings->pixel_clock == 0)
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return -EINVAL;
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is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
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if (dpi_use_dsi_pll(dssdev)) {
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struct dsi_clock_info dsi_cinfo;
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r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft,
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timings->pixel_clock * 1000,
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&dsi_cinfo, &dispc_cinfo);
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if (r)
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return r;
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fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
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} else {
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struct dss_clock_info dss_cinfo;
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r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000,
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&dss_cinfo, &dispc_cinfo);
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if (r)
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return r;
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fck = dss_cinfo.fck;
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}
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lck_div = dispc_cinfo.lck_div;
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pck_div = dispc_cinfo.pck_div;
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pck = fck / lck_div / pck_div / 1000;
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timings->pixel_clock = pck;
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return 0;
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}
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EXPORT_SYMBOL(dpi_check_timings);
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int dpi_init_display(struct omap_dss_device *dssdev)
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{
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DSSDBG("init_display\n");
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if (cpu_is_omap34xx() && dpi.vdds_dsi_reg == NULL) {
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struct regulator *vdds_dsi;
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vdds_dsi = dss_get_vdds_dsi();
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if (IS_ERR(vdds_dsi)) {
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DSSERR("can't get VDDS_DSI regulator\n");
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return PTR_ERR(vdds_dsi);
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}
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dpi.vdds_dsi_reg = vdds_dsi;
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}
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if (dpi_use_dsi_pll(dssdev)) {
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enum omap_dss_clk_source dispc_fclk_src =
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dssdev->clocks.dispc.dispc_fclk_src;
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dpi.dsidev = dpi_get_dsidev(dispc_fclk_src);
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}
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return 0;
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}
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int dpi_init(void)
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{
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return 0;
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}
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void dpi_exit(void)
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{
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}
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