forked from Minki/linux
65f7fa3a3f
Due to the way the composition is done in hardware, we can only have a single alpha-enabled plane active at a time, placed in the second (highest priority) pipe. Make sure of that in our atomic_check to not end up in an impossible scenario. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Link: https://patchwork.freedesktop.org/patch/msgid/7371f62a1385f2cbe3ed75dfca2e746338eb2286.1516617243.git-series.maxime.ripard@free-electrons.com
191 lines
7.2 KiB
C
191 lines
7.2 KiB
C
/*
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* Copyright (C) 2015 Free Electrons
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* Copyright (C) 2015 NextThing Co
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef _SUN4I_BACKEND_H_
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#define _SUN4I_BACKEND_H_
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#include <linux/clk.h>
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#include <linux/list.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include "sunxi_engine.h"
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#define SUN4I_BACKEND_MODCTL_REG 0x800
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#define SUN4I_BACKEND_MODCTL_LINE_SEL BIT(29)
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#define SUN4I_BACKEND_MODCTL_ITLMOD_EN BIT(28)
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#define SUN4I_BACKEND_MODCTL_OUT_SEL GENMASK(22, 20)
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#define SUN4I_BACKEND_MODCTL_OUT_LCD0 (0 << 20)
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#define SUN4I_BACKEND_MODCTL_OUT_LCD1 (1 << 20)
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#define SUN4I_BACKEND_MODCTL_OUT_FE0 (6 << 20)
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#define SUN4I_BACKEND_MODCTL_OUT_FE1 (7 << 20)
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#define SUN4I_BACKEND_MODCTL_HWC_EN BIT(16)
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#define SUN4I_BACKEND_MODCTL_LAY_EN(l) BIT(8 + l)
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#define SUN4I_BACKEND_MODCTL_OCSC_EN BIT(5)
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#define SUN4I_BACKEND_MODCTL_DFLK_EN BIT(4)
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#define SUN4I_BACKEND_MODCTL_DLP_START_CTL BIT(2)
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#define SUN4I_BACKEND_MODCTL_START_CTL BIT(1)
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#define SUN4I_BACKEND_MODCTL_DEBE_EN BIT(0)
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#define SUN4I_BACKEND_BACKCOLOR_REG 0x804
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#define SUN4I_BACKEND_BACKCOLOR(r, g, b) (((r) << 16) | ((g) << 8) | (b))
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#define SUN4I_BACKEND_DISSIZE_REG 0x808
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#define SUN4I_BACKEND_DISSIZE(w, h) (((((h) - 1) & 0xffff) << 16) | \
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(((w) - 1) & 0xffff))
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#define SUN4I_BACKEND_LAYSIZE_REG(l) (0x810 + (0x4 * (l)))
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#define SUN4I_BACKEND_LAYSIZE(w, h) (((((h) - 1) & 0x1fff) << 16) | \
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(((w) - 1) & 0x1fff))
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#define SUN4I_BACKEND_LAYCOOR_REG(l) (0x820 + (0x4 * (l)))
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#define SUN4I_BACKEND_LAYCOOR(x, y) ((((u32)(y) & 0xffff) << 16) | \
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((u32)(x) & 0xffff))
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#define SUN4I_BACKEND_LAYLINEWIDTH_REG(l) (0x840 + (0x4 * (l)))
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#define SUN4I_BACKEND_LAYFB_L32ADD_REG(l) (0x850 + (0x4 * (l)))
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#define SUN4I_BACKEND_LAYFB_H4ADD_REG 0x860
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#define SUN4I_BACKEND_LAYFB_H4ADD_MSK(l) GENMASK(3 + ((l) * 8), (l) * 8)
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#define SUN4I_BACKEND_LAYFB_H4ADD(l, val) ((val) << ((l) * 8))
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#define SUN4I_BACKEND_REGBUFFCTL_REG 0x870
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#define SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS BIT(1)
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#define SUN4I_BACKEND_REGBUFFCTL_LOADCTL BIT(0)
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#define SUN4I_BACKEND_CKMAX_REG 0x880
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#define SUN4I_BACKEND_CKMIN_REG 0x884
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#define SUN4I_BACKEND_CKCFG_REG 0x888
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#define SUN4I_BACKEND_ATTCTL_REG0(l) (0x890 + (0x4 * (l)))
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#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK BIT(15)
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#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(x) ((x) << 15)
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#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK GENMASK(11, 10)
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#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(x) ((x) << 10)
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#define SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN BIT(1)
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#define SUN4I_BACKEND_ATTCTL_REG1(l) (0x8a0 + (0x4 * (l)))
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#define SUN4I_BACKEND_ATTCTL_REG1_LAY_HSCAFCT GENMASK(15, 14)
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#define SUN4I_BACKEND_ATTCTL_REG1_LAY_WSCAFCT GENMASK(13, 12)
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#define SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT GENMASK(11, 8)
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#define SUN4I_BACKEND_LAY_FBFMT_1BPP (0 << 8)
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#define SUN4I_BACKEND_LAY_FBFMT_2BPP (1 << 8)
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#define SUN4I_BACKEND_LAY_FBFMT_4BPP (2 << 8)
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#define SUN4I_BACKEND_LAY_FBFMT_8BPP (3 << 8)
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#define SUN4I_BACKEND_LAY_FBFMT_RGB655 (4 << 8)
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#define SUN4I_BACKEND_LAY_FBFMT_RGB565 (5 << 8)
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#define SUN4I_BACKEND_LAY_FBFMT_RGB556 (6 << 8)
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#define SUN4I_BACKEND_LAY_FBFMT_ARGB1555 (7 << 8)
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#define SUN4I_BACKEND_LAY_FBFMT_RGBA5551 (8 << 8)
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#define SUN4I_BACKEND_LAY_FBFMT_XRGB8888 (9 << 8)
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#define SUN4I_BACKEND_LAY_FBFMT_ARGB8888 (10 << 8)
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#define SUN4I_BACKEND_LAY_FBFMT_RGB888 (11 << 8)
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#define SUN4I_BACKEND_LAY_FBFMT_ARGB4444 (12 << 8)
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#define SUN4I_BACKEND_LAY_FBFMT_RGBA4444 (13 << 8)
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#define SUN4I_BACKEND_DLCDPCTL_REG 0x8b0
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#define SUN4I_BACKEND_DLCDPFRMBUF_ADDRCTL_REG 0x8b4
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#define SUN4I_BACKEND_DLCDPCOOR_REG0 0x8b8
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#define SUN4I_BACKEND_DLCDPCOOR_REG1 0x8bc
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#define SUN4I_BACKEND_INT_EN_REG 0x8c0
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#define SUN4I_BACKEND_INT_FLAG_REG 0x8c4
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#define SUN4I_BACKEND_REG_LOAD_FINISHED BIT(1)
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#define SUN4I_BACKEND_HWCCTL_REG 0x8d8
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#define SUN4I_BACKEND_HWCFBCTL_REG 0x8e0
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#define SUN4I_BACKEND_WBCTL_REG 0x8f0
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#define SUN4I_BACKEND_WBADD_REG 0x8f4
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#define SUN4I_BACKEND_WBLINEWIDTH_REG 0x8f8
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#define SUN4I_BACKEND_SPREN_REG 0x900
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#define SUN4I_BACKEND_SPRFMTCTL_REG 0x908
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#define SUN4I_BACKEND_SPRALPHACTL_REG 0x90c
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#define SUN4I_BACKEND_IYUVCTL_REG 0x920
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#define SUN4I_BACKEND_IYUVADD_REG(c) (0x930 + (0x4 * (c)))
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#define SUN4I_BACKEND_IYUVLINEWIDTH_REG(c) (0x940 + (0x4 * (c)))
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#define SUN4I_BACKEND_YGCOEF_REG(c) (0x950 + (0x4 * (c)))
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#define SUN4I_BACKEND_YGCONS_REG 0x95c
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#define SUN4I_BACKEND_URCOEF_REG(c) (0x960 + (0x4 * (c)))
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#define SUN4I_BACKEND_URCONS_REG 0x96c
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#define SUN4I_BACKEND_VBCOEF_REG(c) (0x970 + (0x4 * (c)))
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#define SUN4I_BACKEND_VBCONS_REG 0x97c
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#define SUN4I_BACKEND_KSCTL_REG 0x980
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#define SUN4I_BACKEND_KSBKCOLOR_REG 0x984
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#define SUN4I_BACKEND_KSFSTLINEWIDTH_REG 0x988
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#define SUN4I_BACKEND_KSVSCAFCT_REG 0x98c
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#define SUN4I_BACKEND_KSHSCACOEF_REG(x) (0x9a0 + (0x4 * (x)))
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#define SUN4I_BACKEND_OCCTL_REG 0x9c0
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#define SUN4I_BACKEND_OCCTL_ENABLE BIT(0)
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#define SUN4I_BACKEND_OCRCOEF_REG(x) (0x9d0 + (0x4 * (x)))
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#define SUN4I_BACKEND_OCRCONS_REG 0x9dc
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#define SUN4I_BACKEND_OCGCOEF_REG(x) (0x9e0 + (0x4 * (x)))
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#define SUN4I_BACKEND_OCGCONS_REG 0x9ec
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#define SUN4I_BACKEND_OCBCOEF_REG(x) (0x9f0 + (0x4 * (x)))
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#define SUN4I_BACKEND_OCBCONS_REG 0x9fc
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#define SUN4I_BACKEND_SPRCOORCTL_REG(s) (0xa00 + (0x4 * (s)))
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#define SUN4I_BACKEND_SPRATTCTL_REG(s) (0xb00 + (0x4 * (s)))
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#define SUN4I_BACKEND_SPRADD_REG(s) (0xc00 + (0x4 * (s)))
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#define SUN4I_BACKEND_SPRLINEWIDTH_REG(s) (0xd00 + (0x4 * (s)))
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#define SUN4I_BACKEND_SPRPALTAB_OFF 0x4000
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#define SUN4I_BACKEND_GAMMATAB_OFF 0x4400
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#define SUN4I_BACKEND_HWCPATTERN_OFF 0x4800
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#define SUN4I_BACKEND_HWCCOLORTAB_OFF 0x4c00
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#define SUN4I_BACKEND_PIPE_OFF(p) (0x5000 + (0x400 * (p)))
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#define SUN4I_BACKEND_NUM_LAYERS 4
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#define SUN4I_BACKEND_NUM_ALPHA_LAYERS 1
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#define SUN4I_BACKEND_NUM_FRONTEND_LAYERS 1
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struct sun4i_backend {
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struct sunxi_engine engine;
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struct sun4i_frontend *frontend;
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struct reset_control *reset;
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struct clk *bus_clk;
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struct clk *mod_clk;
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struct clk *ram_clk;
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struct clk *sat_clk;
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struct reset_control *sat_reset;
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/* Protects against races in the frontend teardown */
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spinlock_t frontend_lock;
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bool frontend_teardown;
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};
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static inline struct sun4i_backend *
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engine_to_sun4i_backend(struct sunxi_engine *engine)
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{
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return container_of(engine, struct sun4i_backend, engine);
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}
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void sun4i_backend_layer_enable(struct sun4i_backend *backend,
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int layer, bool enable);
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int sun4i_backend_update_layer_coord(struct sun4i_backend *backend,
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int layer, struct drm_plane *plane);
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int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
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int layer, struct drm_plane *plane);
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int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
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int layer, struct drm_plane *plane);
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int sun4i_backend_update_layer_frontend(struct sun4i_backend *backend,
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int layer, uint32_t in_fmt);
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int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend,
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int layer, struct drm_plane *plane);
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#endif /* _SUN4I_BACKEND_H_ */
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