forked from Minki/linux
e59451432d
Pinctrl settings for GE0 and GE1 are not only usable on RD-AXPWiFiAP.
Moreover, naming the RGMII settings pmx-ge{0,1} is not precise enough
as there is also a GMII setting for GE0.
Move the pinctrl sub-nodes to the common pinctrl node and rename them
to pmx-ge{0,1}-rgmii.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-By: Benoit Masson <yahoo@perenite.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
229 lines
4.8 KiB
Plaintext
229 lines
4.8 KiB
Plaintext
/*
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* Device Tree Include file for Marvell Armada XP family SoC
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Ben Dooks <ben.dooks@codethink.co.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* Contains definitions specific to the Armada XP SoC that are not
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* common to all Armada SoCs.
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*/
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#include "armada-370-xp.dtsi"
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/ {
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model = "Marvell Armada XP family SoC";
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compatible = "marvell,armadaxp", "marvell,armada-370-xp";
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aliases {
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eth2 = ð2;
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};
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soc {
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compatible = "marvell,armadaxp-mbus", "simple-bus";
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bootrom {
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compatible = "marvell,bootrom";
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reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
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};
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internal-regs {
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L2: l2-cache {
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compatible = "marvell,aurora-system-cache";
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reg = <0x08000 0x1000>;
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cache-id-part = <0x100>;
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cache-unified;
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wt-override;
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};
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i2c0: i2c@11000 {
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compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
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reg = <0x11000 0x100>;
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};
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i2c1: i2c@11100 {
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compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
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reg = <0x11100 0x100>;
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};
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serial@12200 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12200 0x100>;
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reg-shift = <2>;
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interrupts = <43>;
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reg-io-width = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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serial@12300 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12300 0x100>;
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reg-shift = <2>;
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interrupts = <44>;
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reg-io-width = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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pinctrl: pin-ctrl@18000 {
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reg = <0x18000 0x38>;
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pmx_ge0_rgmii: pmx-ge0-rgmii {
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marvell,pins =
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"mpp0", "mpp1", "mpp2", "mpp3",
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"mpp4", "mpp5", "mpp6", "mpp7",
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"mpp8", "mpp9", "mpp10", "mpp11";
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marvell,function = "ge0";
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};
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pmx_ge1_rgmii: pmx-ge1-rgmii {
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marvell,pins =
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"mpp12", "mpp13", "mpp14", "mpp15",
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"mpp16", "mpp17", "mpp18", "mpp19",
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"mpp20", "mpp21", "mpp22", "mpp23";
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marvell,function = "ge1";
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};
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sdio_pins: sdio-pins {
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marvell,pins = "mpp30", "mpp31", "mpp32",
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"mpp33", "mpp34", "mpp35";
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marvell,function = "sd0";
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};
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};
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system-controller@18200 {
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compatible = "marvell,armada-370-xp-system-controller";
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reg = <0x18200 0x500>;
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};
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gateclk: clock-gating-control@18220 {
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compatible = "marvell,armada-xp-gating-clock";
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reg = <0x18220 0x4>;
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clocks = <&coreclk 0>;
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#clock-cells = <1>;
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};
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coreclk: mvebu-sar@18230 {
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compatible = "marvell,armada-xp-core-clock";
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reg = <0x18230 0x08>;
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#clock-cells = <1>;
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};
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thermal@182b0 {
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compatible = "marvell,armadaxp-thermal";
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reg = <0x182b0 0x4
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0x184d0 0x4>;
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status = "okay";
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};
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cpuclk: clock-complex@18700 {
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#clock-cells = <1>;
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compatible = "marvell,armada-xp-cpu-clock";
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reg = <0x18700 0xA0>, <0x1c054 0x10>;
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clocks = <&coreclk 1>;
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};
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interrupt-controller@20000 {
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reg = <0x20a00 0x2d0>, <0x21070 0x58>;
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};
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timer@20300 {
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compatible = "marvell,armada-xp-timer";
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clocks = <&coreclk 2>, <&refclk>;
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clock-names = "nbclk", "fixed";
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};
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watchdog@20300 {
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compatible = "marvell,armada-xp-wdt";
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clocks = <&coreclk 2>, <&refclk>;
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clock-names = "nbclk", "fixed";
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};
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cpurst@20800 {
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compatible = "marvell,armada-370-cpu-reset";
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reg = <0x20800 0x20>;
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};
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eth2: ethernet@30000 {
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compatible = "marvell,armada-370-neta";
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reg = <0x30000 0x4000>;
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interrupts = <12>;
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clocks = <&gateclk 2>;
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status = "disabled";
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};
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usb@50000 {
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clocks = <&gateclk 18>;
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};
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usb@51000 {
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clocks = <&gateclk 19>;
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};
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usb@52000 {
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compatible = "marvell,orion-ehci";
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reg = <0x52000 0x500>;
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interrupts = <47>;
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clocks = <&gateclk 20>;
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status = "disabled";
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};
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xor@60900 {
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compatible = "marvell,orion-xor";
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reg = <0x60900 0x100
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0x60b00 0x100>;
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clocks = <&gateclk 22>;
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status = "okay";
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xor10 {
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interrupts = <51>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor11 {
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interrupts = <52>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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xor@f0900 {
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compatible = "marvell,orion-xor";
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reg = <0xF0900 0x100
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0xF0B00 0x100>;
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clocks = <&gateclk 28>;
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status = "okay";
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xor00 {
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interrupts = <94>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor01 {
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interrupts = <95>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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};
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};
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clocks {
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/* 25 MHz reference crystal */
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refclk: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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};
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};
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