forked from Minki/linux
e57a5f61ea
Add 64-bit ADMA support including: - add 64-bit ADMA descriptor - add SDHCI_USE_64_BIT_DMA flag - set upper 32-bits of DMA addresses - ability to select 64-bit ADMA - ability to use 64-bit ADMA sizes and alignment - display "ADMA 64-bit" when host is added It is assumed that a 64-bit capable device has set a 64-bit DMA mask and *must* do 64-bit DMA. A driver has the opportunity to change that during the first call to ->enable_dma(). Similarly SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to implement. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
463 lines
13 KiB
C
463 lines
13 KiB
C
/*
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* linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
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*
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* Header file for Host Controller registers and I/O accessors.
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*
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* Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#ifndef __SDHCI_HW_H
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#define __SDHCI_HW_H
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#include <linux/scatterlist.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/mmc/sdhci.h>
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/*
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* Controller registers
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*/
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#define SDHCI_DMA_ADDRESS 0x00
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#define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS
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#define SDHCI_BLOCK_SIZE 0x04
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#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
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#define SDHCI_BLOCK_COUNT 0x06
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#define SDHCI_ARGUMENT 0x08
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#define SDHCI_TRANSFER_MODE 0x0C
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#define SDHCI_TRNS_DMA 0x01
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#define SDHCI_TRNS_BLK_CNT_EN 0x02
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#define SDHCI_TRNS_AUTO_CMD12 0x04
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#define SDHCI_TRNS_AUTO_CMD23 0x08
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#define SDHCI_TRNS_READ 0x10
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#define SDHCI_TRNS_MULTI 0x20
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#define SDHCI_COMMAND 0x0E
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#define SDHCI_CMD_RESP_MASK 0x03
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#define SDHCI_CMD_CRC 0x08
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#define SDHCI_CMD_INDEX 0x10
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#define SDHCI_CMD_DATA 0x20
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#define SDHCI_CMD_ABORTCMD 0xC0
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#define SDHCI_CMD_RESP_NONE 0x00
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#define SDHCI_CMD_RESP_LONG 0x01
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#define SDHCI_CMD_RESP_SHORT 0x02
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#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
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#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
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#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
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#define SDHCI_RESPONSE 0x10
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#define SDHCI_BUFFER 0x20
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#define SDHCI_PRESENT_STATE 0x24
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#define SDHCI_CMD_INHIBIT 0x00000001
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#define SDHCI_DATA_INHIBIT 0x00000002
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#define SDHCI_DOING_WRITE 0x00000100
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#define SDHCI_DOING_READ 0x00000200
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#define SDHCI_SPACE_AVAILABLE 0x00000400
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#define SDHCI_DATA_AVAILABLE 0x00000800
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#define SDHCI_CARD_PRESENT 0x00010000
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#define SDHCI_WRITE_PROTECT 0x00080000
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#define SDHCI_DATA_LVL_MASK 0x00F00000
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#define SDHCI_DATA_LVL_SHIFT 20
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#define SDHCI_DATA_0_LVL_MASK 0x00100000
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#define SDHCI_HOST_CONTROL 0x28
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#define SDHCI_CTRL_LED 0x01
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#define SDHCI_CTRL_4BITBUS 0x02
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#define SDHCI_CTRL_HISPD 0x04
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#define SDHCI_CTRL_DMA_MASK 0x18
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#define SDHCI_CTRL_SDMA 0x00
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#define SDHCI_CTRL_ADMA1 0x08
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#define SDHCI_CTRL_ADMA32 0x10
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#define SDHCI_CTRL_ADMA64 0x18
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#define SDHCI_CTRL_8BITBUS 0x20
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#define SDHCI_POWER_CONTROL 0x29
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#define SDHCI_POWER_ON 0x01
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#define SDHCI_POWER_180 0x0A
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#define SDHCI_POWER_300 0x0C
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#define SDHCI_POWER_330 0x0E
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#define SDHCI_BLOCK_GAP_CONTROL 0x2A
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#define SDHCI_WAKE_UP_CONTROL 0x2B
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#define SDHCI_WAKE_ON_INT 0x01
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#define SDHCI_WAKE_ON_INSERT 0x02
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#define SDHCI_WAKE_ON_REMOVE 0x04
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#define SDHCI_CLOCK_CONTROL 0x2C
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#define SDHCI_DIVIDER_SHIFT 8
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#define SDHCI_DIVIDER_HI_SHIFT 6
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#define SDHCI_DIV_MASK 0xFF
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#define SDHCI_DIV_MASK_LEN 8
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#define SDHCI_DIV_HI_MASK 0x300
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#define SDHCI_PROG_CLOCK_MODE 0x0020
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#define SDHCI_CLOCK_CARD_EN 0x0004
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#define SDHCI_CLOCK_INT_STABLE 0x0002
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#define SDHCI_CLOCK_INT_EN 0x0001
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#define SDHCI_TIMEOUT_CONTROL 0x2E
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#define SDHCI_SOFTWARE_RESET 0x2F
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#define SDHCI_RESET_ALL 0x01
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#define SDHCI_RESET_CMD 0x02
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#define SDHCI_RESET_DATA 0x04
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#define SDHCI_INT_STATUS 0x30
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#define SDHCI_INT_ENABLE 0x34
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#define SDHCI_SIGNAL_ENABLE 0x38
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#define SDHCI_INT_RESPONSE 0x00000001
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#define SDHCI_INT_DATA_END 0x00000002
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#define SDHCI_INT_BLK_GAP 0x00000004
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#define SDHCI_INT_DMA_END 0x00000008
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#define SDHCI_INT_SPACE_AVAIL 0x00000010
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#define SDHCI_INT_DATA_AVAIL 0x00000020
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#define SDHCI_INT_CARD_INSERT 0x00000040
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#define SDHCI_INT_CARD_REMOVE 0x00000080
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#define SDHCI_INT_CARD_INT 0x00000100
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#define SDHCI_INT_ERROR 0x00008000
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#define SDHCI_INT_TIMEOUT 0x00010000
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#define SDHCI_INT_CRC 0x00020000
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#define SDHCI_INT_END_BIT 0x00040000
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#define SDHCI_INT_INDEX 0x00080000
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#define SDHCI_INT_DATA_TIMEOUT 0x00100000
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#define SDHCI_INT_DATA_CRC 0x00200000
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#define SDHCI_INT_DATA_END_BIT 0x00400000
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#define SDHCI_INT_BUS_POWER 0x00800000
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#define SDHCI_INT_ACMD12ERR 0x01000000
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#define SDHCI_INT_ADMA_ERROR 0x02000000
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#define SDHCI_INT_NORMAL_MASK 0x00007FFF
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#define SDHCI_INT_ERROR_MASK 0xFFFF8000
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#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
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SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
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#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
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SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
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SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
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SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \
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SDHCI_INT_BLK_GAP)
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#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
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#define SDHCI_ACMD12_ERR 0x3C
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#define SDHCI_HOST_CONTROL2 0x3E
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#define SDHCI_CTRL_UHS_MASK 0x0007
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#define SDHCI_CTRL_UHS_SDR12 0x0000
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#define SDHCI_CTRL_UHS_SDR25 0x0001
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#define SDHCI_CTRL_UHS_SDR50 0x0002
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#define SDHCI_CTRL_UHS_SDR104 0x0003
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#define SDHCI_CTRL_UHS_DDR50 0x0004
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#define SDHCI_CTRL_HS_SDR200 0x0005 /* reserved value in SDIO spec */
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#define SDHCI_CTRL_VDD_180 0x0008
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#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
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#define SDHCI_CTRL_DRV_TYPE_B 0x0000
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#define SDHCI_CTRL_DRV_TYPE_A 0x0010
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#define SDHCI_CTRL_DRV_TYPE_C 0x0020
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#define SDHCI_CTRL_DRV_TYPE_D 0x0030
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#define SDHCI_CTRL_EXEC_TUNING 0x0040
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#define SDHCI_CTRL_TUNED_CLK 0x0080
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#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
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#define SDHCI_CAPABILITIES 0x40
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#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
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#define SDHCI_TIMEOUT_CLK_SHIFT 0
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#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
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#define SDHCI_CLOCK_BASE_MASK 0x00003F00
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#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
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#define SDHCI_CLOCK_BASE_SHIFT 8
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#define SDHCI_MAX_BLOCK_MASK 0x00030000
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#define SDHCI_MAX_BLOCK_SHIFT 16
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#define SDHCI_CAN_DO_8BIT 0x00040000
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#define SDHCI_CAN_DO_ADMA2 0x00080000
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#define SDHCI_CAN_DO_ADMA1 0x00100000
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#define SDHCI_CAN_DO_HISPD 0x00200000
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#define SDHCI_CAN_DO_SDMA 0x00400000
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#define SDHCI_CAN_VDD_330 0x01000000
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#define SDHCI_CAN_VDD_300 0x02000000
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#define SDHCI_CAN_VDD_180 0x04000000
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#define SDHCI_CAN_64BIT 0x10000000
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#define SDHCI_SUPPORT_SDR50 0x00000001
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#define SDHCI_SUPPORT_SDR104 0x00000002
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#define SDHCI_SUPPORT_DDR50 0x00000004
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#define SDHCI_DRIVER_TYPE_A 0x00000010
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#define SDHCI_DRIVER_TYPE_C 0x00000020
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#define SDHCI_DRIVER_TYPE_D 0x00000040
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#define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00
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#define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8
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#define SDHCI_USE_SDR50_TUNING 0x00002000
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#define SDHCI_RETUNING_MODE_MASK 0x0000C000
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#define SDHCI_RETUNING_MODE_SHIFT 14
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#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
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#define SDHCI_CLOCK_MUL_SHIFT 16
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#define SDHCI_CAPABILITIES_1 0x44
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#define SDHCI_MAX_CURRENT 0x48
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#define SDHCI_MAX_CURRENT_LIMIT 0xFF
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#define SDHCI_MAX_CURRENT_330_MASK 0x0000FF
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#define SDHCI_MAX_CURRENT_330_SHIFT 0
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#define SDHCI_MAX_CURRENT_300_MASK 0x00FF00
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#define SDHCI_MAX_CURRENT_300_SHIFT 8
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#define SDHCI_MAX_CURRENT_180_MASK 0xFF0000
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#define SDHCI_MAX_CURRENT_180_SHIFT 16
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#define SDHCI_MAX_CURRENT_MULTIPLIER 4
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/* 4C-4F reserved for more max current */
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#define SDHCI_SET_ACMD12_ERROR 0x50
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#define SDHCI_SET_INT_ERROR 0x52
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#define SDHCI_ADMA_ERROR 0x54
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/* 55-57 reserved */
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#define SDHCI_ADMA_ADDRESS 0x58
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#define SDHCI_ADMA_ADDRESS_HI 0x5C
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/* 60-FB reserved */
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#define SDHCI_PRESET_FOR_SDR12 0x66
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#define SDHCI_PRESET_FOR_SDR25 0x68
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#define SDHCI_PRESET_FOR_SDR50 0x6A
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#define SDHCI_PRESET_FOR_SDR104 0x6C
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#define SDHCI_PRESET_FOR_DDR50 0x6E
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#define SDHCI_PRESET_DRV_MASK 0xC000
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#define SDHCI_PRESET_DRV_SHIFT 14
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#define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400
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#define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10
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#define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF
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#define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0
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#define SDHCI_SLOT_INT_STATUS 0xFC
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#define SDHCI_HOST_VERSION 0xFE
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#define SDHCI_VENDOR_VER_MASK 0xFF00
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#define SDHCI_VENDOR_VER_SHIFT 8
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#define SDHCI_SPEC_VER_MASK 0x00FF
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#define SDHCI_SPEC_VER_SHIFT 0
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#define SDHCI_SPEC_100 0
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#define SDHCI_SPEC_200 1
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#define SDHCI_SPEC_300 2
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/*
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* End of controller registers.
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*/
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#define SDHCI_MAX_DIV_SPEC_200 256
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#define SDHCI_MAX_DIV_SPEC_300 2046
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/*
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* Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
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*/
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#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
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#define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
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/* ADMA2 32-bit DMA descriptor size */
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#define SDHCI_ADMA2_32_DESC_SZ 8
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/* ADMA2 32-bit DMA alignment */
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#define SDHCI_ADMA2_32_ALIGN 4
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/* ADMA2 32-bit descriptor */
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struct sdhci_adma2_32_desc {
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__le16 cmd;
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__le16 len;
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__le32 addr;
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} __packed __aligned(SDHCI_ADMA2_32_ALIGN);
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/* ADMA2 64-bit DMA descriptor size */
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#define SDHCI_ADMA2_64_DESC_SZ 12
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/* ADMA2 64-bit DMA alignment */
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#define SDHCI_ADMA2_64_ALIGN 8
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/*
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* ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
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* aligned.
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*/
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struct sdhci_adma2_64_desc {
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__le16 cmd;
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__le16 len;
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__le32 addr_lo;
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__le32 addr_hi;
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} __packed __aligned(4);
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#define ADMA2_TRAN_VALID 0x21
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#define ADMA2_NOP_END_VALID 0x3
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#define ADMA2_END 0x2
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/*
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* Maximum segments assuming a 512KiB maximum requisition size and a minimum
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* 4KiB page size.
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*/
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#define SDHCI_MAX_SEGS 128
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struct sdhci_ops {
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#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
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u32 (*read_l)(struct sdhci_host *host, int reg);
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u16 (*read_w)(struct sdhci_host *host, int reg);
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u8 (*read_b)(struct sdhci_host *host, int reg);
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void (*write_l)(struct sdhci_host *host, u32 val, int reg);
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void (*write_w)(struct sdhci_host *host, u16 val, int reg);
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void (*write_b)(struct sdhci_host *host, u8 val, int reg);
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#endif
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void (*set_clock)(struct sdhci_host *host, unsigned int clock);
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int (*enable_dma)(struct sdhci_host *host);
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unsigned int (*get_max_clock)(struct sdhci_host *host);
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unsigned int (*get_min_clock)(struct sdhci_host *host);
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unsigned int (*get_timeout_clock)(struct sdhci_host *host);
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unsigned int (*get_max_timeout_count)(struct sdhci_host *host);
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void (*set_timeout)(struct sdhci_host *host,
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struct mmc_command *cmd);
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void (*set_bus_width)(struct sdhci_host *host, int width);
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void (*platform_send_init_74_clocks)(struct sdhci_host *host,
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u8 power_mode);
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unsigned int (*get_ro)(struct sdhci_host *host);
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void (*reset)(struct sdhci_host *host, u8 mask);
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int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
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void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
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void (*hw_reset)(struct sdhci_host *host);
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void (*adma_workaround)(struct sdhci_host *host, u32 intmask);
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void (*platform_init)(struct sdhci_host *host);
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void (*card_event)(struct sdhci_host *host);
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};
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#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
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static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
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{
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if (unlikely(host->ops->write_l))
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host->ops->write_l(host, val, reg);
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else
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writel(val, host->ioaddr + reg);
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}
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static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
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{
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if (unlikely(host->ops->write_w))
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host->ops->write_w(host, val, reg);
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else
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writew(val, host->ioaddr + reg);
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}
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static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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if (unlikely(host->ops->write_b))
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host->ops->write_b(host, val, reg);
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else
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writeb(val, host->ioaddr + reg);
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}
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static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
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{
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if (unlikely(host->ops->read_l))
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return host->ops->read_l(host, reg);
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else
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return readl(host->ioaddr + reg);
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}
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static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
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{
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if (unlikely(host->ops->read_w))
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return host->ops->read_w(host, reg);
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else
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return readw(host->ioaddr + reg);
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}
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static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
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{
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if (unlikely(host->ops->read_b))
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return host->ops->read_b(host, reg);
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else
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return readb(host->ioaddr + reg);
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}
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#else
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static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
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{
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writel(val, host->ioaddr + reg);
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}
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static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
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{
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writew(val, host->ioaddr + reg);
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}
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static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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writeb(val, host->ioaddr + reg);
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}
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static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
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{
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return readl(host->ioaddr + reg);
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}
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static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
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{
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return readw(host->ioaddr + reg);
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}
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static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
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{
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return readb(host->ioaddr + reg);
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}
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#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
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extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
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size_t priv_size);
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extern void sdhci_free_host(struct sdhci_host *host);
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static inline void *sdhci_priv(struct sdhci_host *host)
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{
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return (void *)host->private;
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}
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extern void sdhci_card_detect(struct sdhci_host *host);
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extern int sdhci_add_host(struct sdhci_host *host);
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extern void sdhci_remove_host(struct sdhci_host *host, int dead);
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extern void sdhci_send_command(struct sdhci_host *host,
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struct mmc_command *cmd);
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|
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static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host)
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|
{
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return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED);
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}
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void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
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void sdhci_set_bus_width(struct sdhci_host *host, int width);
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void sdhci_reset(struct sdhci_host *host, u8 mask);
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void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
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|
|
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#ifdef CONFIG_PM
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extern int sdhci_suspend_host(struct sdhci_host *host);
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extern int sdhci_resume_host(struct sdhci_host *host);
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extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
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#endif
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|
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|
#ifdef CONFIG_PM_RUNTIME
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extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
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extern int sdhci_runtime_resume_host(struct sdhci_host *host);
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#endif
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|
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#endif /* __SDHCI_HW_H */
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