04d5d5df9d
Display controller (DC) performs isochronous memory transfers, and thus, has a requirement for a minimum memory bandwidth that shall be fulfilled, otherwise framebuffer data can't be fetched fast enough and this results in a DC's data-FIFO underflow that follows by a visual corruption. The Memory Controller drivers provide facility for memory bandwidth management via interconnect API. Let's wire up the interconnect API support to the DC driver in order to fix the distorted display output on T30 Ouya, T124 TK1 and other Tegra devices. Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> [treding@nvidia.com: unbreak Tegra186+ display support] Signed-off-by: Thierry Reding <treding@nvidia.com>
37 lines
810 B
Plaintext
37 lines
810 B
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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config DRM_TEGRA
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tristate "NVIDIA Tegra DRM"
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depends on ARCH_TEGRA || (ARM && COMPILE_TEST)
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depends on COMMON_CLK
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depends on DRM
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depends on OF
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select DRM_KMS_HELPER
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select DRM_MIPI_DSI
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select DRM_PANEL
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select TEGRA_HOST1X
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select INTERCONNECT
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select IOMMU_IOVA
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select CEC_CORE if CEC_NOTIFIER
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help
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Choose this option if you have an NVIDIA Tegra SoC.
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To compile this driver as a module, choose M here: the module
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will be called tegra-drm.
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if DRM_TEGRA
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config DRM_TEGRA_DEBUG
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bool "NVIDIA Tegra DRM debug support"
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help
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Say yes here to enable debugging support.
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config DRM_TEGRA_STAGING
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bool "Enable HOST1X interface"
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depends on STAGING
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help
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Say yes if HOST1X should be available for userspace DRM users.
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If unsure, choose N.
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endif
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