forked from Minki/linux
bcb24f6577
The current default for async hw receive queues is 1, which presents issues under heavy load as number of queues influence the available async receive buffer limits. Raise the default to the either the current hw limit (16) or the number of hw qs configured (io channel value). Revise the attribute definition for mrq to better reflect what we do for hw queues. E.g. 0 means default to optimal (# of cpus), non-zero specifies a specific limit. Before this change, mrq=0 meant target mode was disabled. As 0 now has a different meaning, rework the if tests to use the better nvmet_support check. Signed-off-by: Dick Kennedy <dick.kennedy@broadcom.com> Signed-off-by: James Smart <james.smart@broadcom.com> Reviewed-by: Hannes Reinecke <hare@suse.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
145 lines
4.7 KiB
C
145 lines
4.7 KiB
C
/*******************************************************************
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* This file is part of the Emulex Linux Device Driver for *
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* Fibre Channel Host Bus Adapters. *
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* Copyright (C) 2017 Broadcom. All Rights Reserved. The term *
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* “Broadcom” refers to Broadcom Limited and/or its subsidiaries. *
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* Copyright (C) 2004-2016 Emulex. All rights reserved. *
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* EMULEX and SLI are trademarks of Emulex. *
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* www.broadcom.com *
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* Portions Copyright (C) 2004-2005 Christoph Hellwig *
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* *
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* This program is free software; you can redistribute it and/or *
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* modify it under the terms of version 2 of the GNU General *
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* Public License as published by the Free Software Foundation. *
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* This program is distributed in the hope that it will be useful. *
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* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
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* WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
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* DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
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* TO BE LEGALLY INVALID. See the GNU General Public License for *
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* more details, a copy of which can be found in the file COPYING *
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* included with this package. *
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********************************************************************/
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#define LPFC_NVMET_DEFAULT_SEGS (64 + 1) /* 256K IOs */
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#define LPFC_NVMET_RQE_DEF_COUNT 512
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#define LPFC_NVMET_SUCCESS_LEN 12
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#define LPFC_NVMET_MRQ_OFF 0xffff
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#define LPFC_NVMET_MRQ_AUTO 0
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#define LPFC_NVMET_MRQ_MAX 16
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/* Used for NVME Target */
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struct lpfc_nvmet_tgtport {
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struct lpfc_hba *phba;
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struct completion tport_unreg_done;
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/* Stats counters - lpfc_nvmet_unsol_ls_buffer */
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atomic_t rcv_ls_req_in;
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atomic_t rcv_ls_req_out;
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atomic_t rcv_ls_req_drop;
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atomic_t xmt_ls_abort;
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atomic_t xmt_ls_abort_cmpl;
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/* Stats counters - lpfc_nvmet_xmt_ls_rsp */
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atomic_t xmt_ls_rsp;
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atomic_t xmt_ls_drop;
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/* Stats counters - lpfc_nvmet_xmt_ls_rsp_cmp */
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atomic_t xmt_ls_rsp_error;
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atomic_t xmt_ls_rsp_cmpl;
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/* Stats counters - lpfc_nvmet_unsol_fcp_buffer */
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atomic_t rcv_fcp_cmd_in;
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atomic_t rcv_fcp_cmd_out;
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atomic_t rcv_fcp_cmd_drop;
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atomic_t rcv_fcp_cmd_defer;
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atomic_t xmt_fcp_release;
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/* Stats counters - lpfc_nvmet_xmt_fcp_op */
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atomic_t xmt_fcp_drop;
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atomic_t xmt_fcp_read_rsp;
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atomic_t xmt_fcp_read;
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atomic_t xmt_fcp_write;
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atomic_t xmt_fcp_rsp;
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/* Stats counters - lpfc_nvmet_xmt_fcp_op_cmp */
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atomic_t xmt_fcp_rsp_cmpl;
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atomic_t xmt_fcp_rsp_error;
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atomic_t xmt_fcp_rsp_drop;
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/* Stats counters - lpfc_nvmet_xmt_fcp_abort */
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atomic_t xmt_fcp_abort;
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atomic_t xmt_fcp_abort_cmpl;
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atomic_t xmt_abort_sol;
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atomic_t xmt_abort_unsol;
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atomic_t xmt_abort_rsp;
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atomic_t xmt_abort_rsp_error;
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};
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struct lpfc_nvmet_ctx_info {
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struct list_head nvmet_ctx_list;
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spinlock_t nvmet_ctx_list_lock; /* lock per CPU */
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struct lpfc_nvmet_ctx_info *nvmet_ctx_next_cpu;
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struct lpfc_nvmet_ctx_info *nvmet_ctx_start_cpu;
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uint16_t nvmet_ctx_list_cnt;
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char pad[16]; /* pad to a cache-line */
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};
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/* This retrieves the context info associated with the specified cpu / mrq */
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#define lpfc_get_ctx_list(phba, cpu, mrq) \
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(phba->sli4_hba.nvmet_ctx_info + ((cpu * phba->cfg_nvmet_mrq) + mrq))
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struct lpfc_nvmet_rcv_ctx {
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union {
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struct nvmefc_tgt_ls_req ls_req;
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struct nvmefc_tgt_fcp_req fcp_req;
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} ctx;
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struct list_head list;
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struct lpfc_hba *phba;
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struct lpfc_iocbq *wqeq;
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struct lpfc_iocbq *abort_wqeq;
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dma_addr_t txrdy_phys;
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spinlock_t ctxlock; /* protect flag access */
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uint32_t *txrdy;
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uint32_t sid;
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uint32_t offset;
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uint16_t oxid;
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uint16_t size;
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uint16_t entry_cnt;
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uint16_t cpu;
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uint16_t idx;
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uint16_t state;
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/* States */
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#define LPFC_NVMET_STE_LS_RCV 1
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#define LPFC_NVMET_STE_LS_ABORT 2
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#define LPFC_NVMET_STE_LS_RSP 3
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#define LPFC_NVMET_STE_RCV 4
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#define LPFC_NVMET_STE_DATA 5
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#define LPFC_NVMET_STE_ABORT 6
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#define LPFC_NVMET_STE_DONE 7
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#define LPFC_NVMET_STE_FREE 0xff
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uint16_t flag;
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#define LPFC_NVMET_IO_INP 0x1 /* IO is in progress on exchange */
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#define LPFC_NVMET_ABORT_OP 0x2 /* Abort WQE issued on exchange */
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#define LPFC_NVMET_XBUSY 0x4 /* XB bit set on IO cmpl */
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#define LPFC_NVMET_CTX_RLS 0x8 /* ctx free requested */
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#define LPFC_NVMET_ABTS_RCV 0x10 /* ABTS received on exchange */
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struct rqb_dmabuf *rqb_buffer;
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struct lpfc_nvmet_ctxbuf *ctxbuf;
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#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
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uint64_t ts_isr_cmd;
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uint64_t ts_cmd_nvme;
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uint64_t ts_nvme_data;
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uint64_t ts_data_wqput;
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uint64_t ts_isr_data;
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uint64_t ts_data_nvme;
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uint64_t ts_nvme_status;
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uint64_t ts_status_wqput;
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uint64_t ts_isr_status;
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uint64_t ts_status_nvme;
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#endif
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};
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