forked from Minki/linux
e44b7b7525
Move wakeup code to .c, so that video mode setting code can be shared between boot and wakeup. Remove nasty assembly code in 64-bit case by re-using trampoline code. Stack setup was fixed to clear high 16bits of %esp, maybe that fixes some machines. .c code sharing and morse code was done H. Peter Anvin, Sam Ravnborg reviewed kbuild related stuff, and it seems okay to him. Rafael did some cleanups. [rjw: * Made the patch stop breaking compilation on x86-32 * Added arch/x86/kernel/acpi/sleep.h * Got rid of compiler warnings in arch/x86/kernel/acpi/sleep.c * Fixed 32-bit compilation on x86-64 systems * Added include/asm-x86/trampoline.h and fixed the non-SMP compilation on 64-bit x86 * Removed arch/x86/kernel/acpi/sleep_32.c which was not used * Fixed some breakage caused by the integration of smpboot.c done under us in the meantime] Signed-off-by: Pavel Machek <pavel@suse.cz> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Ingo Molnar <mingo@elte.hu>
455 lines
11 KiB
ArmAsm
455 lines
11 KiB
ArmAsm
/*
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* linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
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*
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* Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
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* Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
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* Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
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* Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
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* Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
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*/
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#include <linux/linkage.h>
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#include <linux/threads.h>
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#include <linux/init.h>
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#include <asm/desc.h>
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#include <asm/segment.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/msr.h>
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#include <asm/cache.h>
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#ifdef CONFIG_PARAVIRT
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#include <asm/asm-offsets.h>
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#include <asm/paravirt.h>
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#else
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#define GET_CR2_INTO_RCX movq %cr2, %rcx
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#endif
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/* we are not able to switch in one step to the final KERNEL ADRESS SPACE
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* because we need identity-mapped pages.
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*
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*/
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.text
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.section .text.head
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.code64
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.globl startup_64
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startup_64:
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/*
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* At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
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* and someone has loaded an identity mapped page table
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* for us. These identity mapped page tables map all of the
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* kernel pages and possibly all of memory.
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*
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* %esi holds a physical pointer to real_mode_data.
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*
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* We come here either directly from a 64bit bootloader, or from
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* arch/x86_64/boot/compressed/head.S.
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*
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* We only come here initially at boot nothing else comes here.
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*
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* Since we may be loaded at an address different from what we were
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* compiled to run at we first fixup the physical addresses in our page
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* tables and then reload them.
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*/
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/* Compute the delta between the address I am compiled to run at and the
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* address I am actually running at.
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*/
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leaq _text(%rip), %rbp
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subq $_text - __START_KERNEL_map, %rbp
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/* Is the address not 2M aligned? */
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movq %rbp, %rax
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andl $~PMD_PAGE_MASK, %eax
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testl %eax, %eax
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jnz bad_address
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/* Is the address too large? */
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leaq _text(%rip), %rdx
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movq $PGDIR_SIZE, %rax
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cmpq %rax, %rdx
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jae bad_address
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/* Fixup the physical addresses in the page table
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*/
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addq %rbp, init_level4_pgt + 0(%rip)
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addq %rbp, init_level4_pgt + (258*8)(%rip)
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addq %rbp, init_level4_pgt + (511*8)(%rip)
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addq %rbp, level3_ident_pgt + 0(%rip)
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addq %rbp, level3_kernel_pgt + (510*8)(%rip)
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addq %rbp, level3_kernel_pgt + (511*8)(%rip)
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addq %rbp, level2_fixmap_pgt + (506*8)(%rip)
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/* Add an Identity mapping if I am above 1G */
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leaq _text(%rip), %rdi
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andq $PMD_PAGE_MASK, %rdi
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movq %rdi, %rax
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shrq $PUD_SHIFT, %rax
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andq $(PTRS_PER_PUD - 1), %rax
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jz ident_complete
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leaq (level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx
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leaq level3_ident_pgt(%rip), %rbx
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movq %rdx, 0(%rbx, %rax, 8)
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movq %rdi, %rax
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shrq $PMD_SHIFT, %rax
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andq $(PTRS_PER_PMD - 1), %rax
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leaq __PAGE_KERNEL_LARGE_EXEC(%rdi), %rdx
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leaq level2_spare_pgt(%rip), %rbx
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movq %rdx, 0(%rbx, %rax, 8)
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ident_complete:
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/*
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* Fixup the kernel text+data virtual addresses. Note that
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* we might write invalid pmds, when the kernel is relocated
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* cleanup_highmap() fixes this up along with the mappings
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* beyond _end.
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*/
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leaq level2_kernel_pgt(%rip), %rdi
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leaq 4096(%rdi), %r8
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/* See if it is a valid page table entry */
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1: testq $1, 0(%rdi)
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jz 2f
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addq %rbp, 0(%rdi)
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/* Go to the next page */
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2: addq $8, %rdi
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cmp %r8, %rdi
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jne 1b
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/* Fixup phys_base */
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addq %rbp, phys_base(%rip)
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#ifdef CONFIG_SMP
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addq %rbp, trampoline_level4_pgt + 0(%rip)
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addq %rbp, trampoline_level4_pgt + (511*8)(%rip)
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#endif
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/* Due to ENTRY(), sometimes the empty space gets filled with
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* zeros. Better take a jmp than relying on empty space being
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* filled with 0x90 (nop)
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*/
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jmp secondary_startup_64
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ENTRY(secondary_startup_64)
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/*
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* At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
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* and someone has loaded a mapped page table.
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*
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* %esi holds a physical pointer to real_mode_data.
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*
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* We come here either from startup_64 (using physical addresses)
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* or from trampoline.S (using virtual addresses).
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*
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* Using virtual addresses from trampoline.S removes the need
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* to have any identity mapped pages in the kernel page table
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* after the boot processor executes this code.
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*/
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/* Enable PAE mode and PGE */
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xorq %rax, %rax
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btsq $5, %rax
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btsq $7, %rax
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movq %rax, %cr4
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/* Setup early boot stage 4 level pagetables. */
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movq $(init_level4_pgt - __START_KERNEL_map), %rax
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addq phys_base(%rip), %rax
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movq %rax, %cr3
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/* Ensure I am executing from virtual addresses */
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movq $1f, %rax
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jmp *%rax
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1:
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/* Check if nx is implemented */
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movl $0x80000001, %eax
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cpuid
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movl %edx,%edi
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/* Setup EFER (Extended Feature Enable Register) */
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movl $MSR_EFER, %ecx
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rdmsr
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btsl $_EFER_SCE, %eax /* Enable System Call */
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btl $20,%edi /* No Execute supported? */
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jnc 1f
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btsl $_EFER_NX, %eax
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1: wrmsr /* Make changes effective */
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/* Setup cr0 */
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#define CR0_PM 1 /* protected mode */
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#define CR0_MP (1<<1)
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#define CR0_ET (1<<4)
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#define CR0_NE (1<<5)
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#define CR0_WP (1<<16)
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#define CR0_AM (1<<18)
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#define CR0_PAGING (1<<31)
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movl $CR0_PM|CR0_MP|CR0_ET|CR0_NE|CR0_WP|CR0_AM|CR0_PAGING,%eax
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/* Make changes effective */
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movq %rax, %cr0
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/* Setup a boot time stack */
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movq init_rsp(%rip),%rsp
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/* zero EFLAGS after setting rsp */
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pushq $0
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popfq
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/*
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* We must switch to a new descriptor in kernel space for the GDT
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* because soon the kernel won't have access anymore to the userspace
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* addresses where we're currently running on. We have to do that here
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* because in 32bit we couldn't load a 64bit linear address.
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*/
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lgdt cpu_gdt_descr(%rip)
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/* set up data segments. actually 0 would do too */
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movl $__KERNEL_DS,%eax
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movl %eax,%ds
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movl %eax,%ss
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movl %eax,%es
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/*
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* We don't really need to load %fs or %gs, but load them anyway
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* to kill any stale realmode selectors. This allows execution
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* under VT hardware.
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*/
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movl %eax,%fs
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movl %eax,%gs
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/*
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* Setup up a dummy PDA. this is just for some early bootup code
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* that does in_interrupt()
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*/
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movl $MSR_GS_BASE,%ecx
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movq $empty_zero_page,%rax
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movq %rax,%rdx
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shrq $32,%rdx
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wrmsr
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/* esi is pointer to real mode structure with interesting info.
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pass it to C */
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movl %esi, %edi
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/* Finally jump to run C code and to be on real kernel address
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* Since we are running on identity-mapped space we have to jump
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* to the full 64bit address, this is only possible as indirect
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* jump. In addition we need to ensure %cs is set so we make this
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* a far return.
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*/
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movq initial_code(%rip),%rax
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pushq $0 # fake return address to stop unwinder
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pushq $__KERNEL_CS # set correct cs
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pushq %rax # target address in negative space
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lretq
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/* SMP bootup changes these two */
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__REFDATA
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.align 8
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ENTRY(initial_code)
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.quad x86_64_start_kernel
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__FINITDATA
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ENTRY(init_rsp)
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.quad init_thread_union+THREAD_SIZE-8
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bad_address:
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jmp bad_address
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.section ".init.text","ax"
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#ifdef CONFIG_EARLY_PRINTK
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.globl early_idt_handlers
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early_idt_handlers:
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i = 0
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.rept NUM_EXCEPTION_VECTORS
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movl $i, %esi
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jmp early_idt_handler
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i = i + 1
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.endr
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#endif
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ENTRY(early_idt_handler)
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#ifdef CONFIG_EARLY_PRINTK
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cmpl $2,early_recursion_flag(%rip)
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jz 1f
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incl early_recursion_flag(%rip)
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GET_CR2_INTO_RCX
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movq %rcx,%r9
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xorl %r8d,%r8d # zero for error code
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movl %esi,%ecx # get vector number
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# Test %ecx against mask of vectors that push error code.
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cmpl $31,%ecx
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ja 0f
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movl $1,%eax
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salq %cl,%rax
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testl $0x27d00,%eax
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je 0f
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popq %r8 # get error code
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0: movq 0(%rsp),%rcx # get ip
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movq 8(%rsp),%rdx # get cs
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xorl %eax,%eax
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leaq early_idt_msg(%rip),%rdi
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call early_printk
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cmpl $2,early_recursion_flag(%rip)
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jz 1f
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call dump_stack
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#ifdef CONFIG_KALLSYMS
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leaq early_idt_ripmsg(%rip),%rdi
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movq 8(%rsp),%rsi # get rip again
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call __print_symbol
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#endif
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#endif /* EARLY_PRINTK */
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1: hlt
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jmp 1b
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#ifdef CONFIG_EARLY_PRINTK
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early_recursion_flag:
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.long 0
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early_idt_msg:
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.asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n"
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early_idt_ripmsg:
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.asciz "RIP %s\n"
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#endif /* CONFIG_EARLY_PRINTK */
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.previous
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.balign PAGE_SIZE
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#define NEXT_PAGE(name) \
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.balign PAGE_SIZE; \
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ENTRY(name)
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/* Automate the creation of 1 to 1 mapping pmd entries */
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#define PMDS(START, PERM, COUNT) \
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i = 0 ; \
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.rept (COUNT) ; \
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.quad (START) + (i << 21) + (PERM) ; \
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i = i + 1 ; \
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.endr
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/*
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* This default setting generates an ident mapping at address 0x100000
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* and a mapping for the kernel that precisely maps virtual address
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* 0xffffffff80000000 to physical address 0x000000. (always using
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* 2Mbyte large pages provided by PAE mode)
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*/
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NEXT_PAGE(init_level4_pgt)
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.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
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.fill 257,8,0
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.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
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.fill 252,8,0
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/* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
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.quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
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NEXT_PAGE(level3_ident_pgt)
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.quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
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.fill 511,8,0
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NEXT_PAGE(level3_kernel_pgt)
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.fill 510,8,0
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/* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
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.quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
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.quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
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NEXT_PAGE(level2_fixmap_pgt)
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.fill 506,8,0
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.quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
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/* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
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.fill 5,8,0
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NEXT_PAGE(level1_fixmap_pgt)
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.fill 512,8,0
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NEXT_PAGE(level2_ident_pgt)
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/* Since I easily can, map the first 1G.
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* Don't set NX because code runs from these pages.
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*/
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PMDS(0, __PAGE_KERNEL_LARGE_EXEC, PTRS_PER_PMD)
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NEXT_PAGE(level2_kernel_pgt)
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/*
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* 512 MB kernel mapping. We spend a full page on this pagetable
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* anyway.
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*
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* The kernel code+data+bss must not be bigger than that.
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*
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* (NOTE: at +512MB starts the module area, see MODULES_VADDR.
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* If you want to increase this then increase MODULES_VADDR
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* too.)
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*/
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PMDS(0, __PAGE_KERNEL_LARGE_EXEC|_PAGE_GLOBAL,
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KERNEL_IMAGE_SIZE/PMD_SIZE)
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NEXT_PAGE(level2_spare_pgt)
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.fill 512, 8, 0
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#undef PMDS
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#undef NEXT_PAGE
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.data
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.align 16
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.globl cpu_gdt_descr
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cpu_gdt_descr:
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.word gdt_end-cpu_gdt_table-1
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gdt:
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.quad cpu_gdt_table
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#ifdef CONFIG_SMP
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.rept NR_CPUS-1
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.word 0
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.quad 0
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.endr
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#endif
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ENTRY(phys_base)
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/* This must match the first entry in level2_kernel_pgt */
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.quad 0x0000000000000000
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/* We need valid kernel segments for data and code in long mode too
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* IRET will check the segment types kkeil 2000/10/28
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* Also sysret mandates a special GDT layout
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*/
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.section .data.page_aligned, "aw"
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.align PAGE_SIZE
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/* The TLS descriptors are currently at a different place compared to i386.
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Hopefully nobody expects them at a fixed place (Wine?) */
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ENTRY(cpu_gdt_table)
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.quad 0x0000000000000000 /* NULL descriptor */
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.quad 0x00cf9b000000ffff /* __KERNEL32_CS */
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.quad 0x00af9b000000ffff /* __KERNEL_CS */
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.quad 0x00cf93000000ffff /* __KERNEL_DS */
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.quad 0x00cffb000000ffff /* __USER32_CS */
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.quad 0x00cff3000000ffff /* __USER_DS, __USER32_DS */
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.quad 0x00affb000000ffff /* __USER_CS */
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.quad 0x0 /* unused */
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.quad 0,0 /* TSS */
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.quad 0,0 /* LDT */
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.quad 0,0,0 /* three TLS descriptors */
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.quad 0x0000f40000000000 /* node/CPU stored in limit */
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gdt_end:
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/* asm/segment.h:GDT_ENTRIES must match this */
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/* This should be a multiple of the cache line size */
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/* GDTs of other CPUs are now dynamically allocated */
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/* zero the remaining page */
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.fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0
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.section .bss, "aw", @nobits
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.align L1_CACHE_BYTES
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ENTRY(idt_table)
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.skip 256 * 16
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.section .bss.page_aligned, "aw", @nobits
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.align PAGE_SIZE
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ENTRY(empty_zero_page)
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.skip PAGE_SIZE
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