forked from Minki/linux
669f78802b
Add LLCC configuration data for SC7180 SoC which controls LLCC behaviour. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
517 lines
14 KiB
C
517 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
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*
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*/
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#include <linux/bitmap.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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#include <linux/sizes.h>
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#include <linux/slab.h>
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#include <linux/soc/qcom/llcc-qcom.h>
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#define ACTIVATE BIT(0)
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#define DEACTIVATE BIT(1)
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#define ACT_CTRL_OPCODE_ACTIVATE BIT(0)
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#define ACT_CTRL_OPCODE_DEACTIVATE BIT(1)
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#define ACT_CTRL_ACT_TRIG BIT(0)
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#define ACT_CTRL_OPCODE_SHIFT 0x01
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#define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02
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#define ATTR1_FIXED_SIZE_SHIFT 0x03
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#define ATTR1_PRIORITY_SHIFT 0x04
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#define ATTR1_MAX_CAP_SHIFT 0x10
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#define ATTR0_RES_WAYS_MASK GENMASK(11, 0)
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#define ATTR0_BONUS_WAYS_MASK GENMASK(27, 16)
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#define ATTR0_BONUS_WAYS_SHIFT 0x10
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#define LLCC_STATUS_READ_DELAY 100
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#define CACHE_LINE_SIZE_SHIFT 6
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#define LLCC_COMMON_STATUS0 0x0003000c
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#define LLCC_LB_CNT_MASK GENMASK(31, 28)
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#define LLCC_LB_CNT_SHIFT 28
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#define MAX_CAP_TO_BYTES(n) (n * SZ_1K)
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#define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K)
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#define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K)
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#define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n)
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#define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n)
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#define BANK_OFFSET_STRIDE 0x80000
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/**
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* llcc_slice_config - Data associated with the llcc slice
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* @usecase_id: Unique id for the client's use case
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* @slice_id: llcc slice id for each client
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* @max_cap: The maximum capacity of the cache slice provided in KB
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* @priority: Priority of the client used to select victim line for replacement
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* @fixed_size: Boolean indicating if the slice has a fixed capacity
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* @bonus_ways: Bonus ways are additional ways to be used for any slice,
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* if client ends up using more than reserved cache ways. Bonus
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* ways are allocated only if they are not reserved for some
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* other client.
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* @res_ways: Reserved ways for the cache slice, the reserved ways cannot
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* be used by any other client than the one its assigned to.
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* @cache_mode: Each slice operates as a cache, this controls the mode of the
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* slice: normal or TCM(Tightly Coupled Memory)
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* @probe_target_ways: Determines what ways to probe for access hit. When
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* configured to 1 only bonus and reserved ways are probed.
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* When configured to 0 all ways in llcc are probed.
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* @dis_cap_alloc: Disable capacity based allocation for a client
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* @retain_on_pc: If this bit is set and client has maintained active vote
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* then the ways assigned to this client are not flushed on power
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* collapse.
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* @activate_on_init: Activate the slice immediately after it is programmed
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*/
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struct llcc_slice_config {
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u32 usecase_id;
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u32 slice_id;
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u32 max_cap;
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u32 priority;
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bool fixed_size;
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u32 bonus_ways;
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u32 res_ways;
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u32 cache_mode;
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u32 probe_target_ways;
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bool dis_cap_alloc;
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bool retain_on_pc;
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bool activate_on_init;
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};
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struct qcom_llcc_config {
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const struct llcc_slice_config *sct_data;
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int size;
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};
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static const struct llcc_slice_config sc7180_data[] = {
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{ LLCC_CPUSS, 1, 256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 },
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{ LLCC_MDM, 8, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
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{ LLCC_GPUHTW, 11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
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{ LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
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};
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static const struct llcc_slice_config sdm845_data[] = {
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{ LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 },
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{ LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 },
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{ LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 },
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{ LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0 },
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{ LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
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{ LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
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{ LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0 },
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{ LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
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{ LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
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{ LLCC_GPUHTW, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0 },
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{ LLCC_GPU, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0 },
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{ LLCC_MMUHWT, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1 },
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{ LLCC_CMPTDMA, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
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{ LLCC_DISP, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
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{ LLCC_VIDFW, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
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{ LLCC_MDMHPFX, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0 },
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{ LLCC_MDMPNG, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0 },
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{ LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 },
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};
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static const struct qcom_llcc_config sc7180_cfg = {
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.sct_data = sc7180_data,
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.size = ARRAY_SIZE(sc7180_data),
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};
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static const struct qcom_llcc_config sdm845_cfg = {
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.sct_data = sdm845_data,
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.size = ARRAY_SIZE(sdm845_data),
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};
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static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
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/**
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* llcc_slice_getd - get llcc slice descriptor
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* @uid: usecase_id for the client
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*
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* A pointer to llcc slice descriptor will be returned on success and
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* and error pointer is returned on failure
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*/
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struct llcc_slice_desc *llcc_slice_getd(u32 uid)
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{
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const struct llcc_slice_config *cfg;
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struct llcc_slice_desc *desc;
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u32 sz, count;
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if (IS_ERR(drv_data))
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return ERR_CAST(drv_data);
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cfg = drv_data->cfg;
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sz = drv_data->cfg_size;
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for (count = 0; cfg && count < sz; count++, cfg++)
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if (cfg->usecase_id == uid)
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break;
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if (count == sz || !cfg)
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return ERR_PTR(-ENODEV);
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desc = kzalloc(sizeof(*desc), GFP_KERNEL);
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if (!desc)
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return ERR_PTR(-ENOMEM);
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desc->slice_id = cfg->slice_id;
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desc->slice_size = cfg->max_cap;
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return desc;
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}
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EXPORT_SYMBOL_GPL(llcc_slice_getd);
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/**
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* llcc_slice_putd - llcc slice descritpor
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* @desc: Pointer to llcc slice descriptor
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*/
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void llcc_slice_putd(struct llcc_slice_desc *desc)
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{
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if (!IS_ERR_OR_NULL(desc))
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kfree(desc);
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}
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EXPORT_SYMBOL_GPL(llcc_slice_putd);
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static int llcc_update_act_ctrl(u32 sid,
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u32 act_ctrl_reg_val, u32 status)
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{
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u32 act_ctrl_reg;
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u32 status_reg;
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u32 slice_status;
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int ret;
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if (IS_ERR(drv_data))
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return PTR_ERR(drv_data);
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act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid);
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status_reg = LLCC_TRP_STATUSn(sid);
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/* Set the ACTIVE trigger */
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act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG;
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ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
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act_ctrl_reg_val);
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if (ret)
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return ret;
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/* Clear the ACTIVE trigger */
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act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG;
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ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
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act_ctrl_reg_val);
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if (ret)
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return ret;
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ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg,
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slice_status, !(slice_status & status),
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0, LLCC_STATUS_READ_DELAY);
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return ret;
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}
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/**
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* llcc_slice_activate - Activate the llcc slice
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* @desc: Pointer to llcc slice descriptor
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*
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* A value of zero will be returned on success and a negative errno will
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* be returned in error cases
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*/
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int llcc_slice_activate(struct llcc_slice_desc *desc)
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{
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int ret;
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u32 act_ctrl_val;
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if (IS_ERR(drv_data))
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return PTR_ERR(drv_data);
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if (IS_ERR_OR_NULL(desc))
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return -EINVAL;
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mutex_lock(&drv_data->lock);
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if (test_bit(desc->slice_id, drv_data->bitmap)) {
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mutex_unlock(&drv_data->lock);
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return 0;
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}
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act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT;
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ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
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DEACTIVATE);
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if (ret) {
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mutex_unlock(&drv_data->lock);
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return ret;
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}
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__set_bit(desc->slice_id, drv_data->bitmap);
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mutex_unlock(&drv_data->lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(llcc_slice_activate);
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/**
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* llcc_slice_deactivate - Deactivate the llcc slice
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* @desc: Pointer to llcc slice descriptor
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*
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* A value of zero will be returned on success and a negative errno will
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* be returned in error cases
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*/
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int llcc_slice_deactivate(struct llcc_slice_desc *desc)
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{
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u32 act_ctrl_val;
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int ret;
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if (IS_ERR(drv_data))
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return PTR_ERR(drv_data);
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if (IS_ERR_OR_NULL(desc))
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return -EINVAL;
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mutex_lock(&drv_data->lock);
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if (!test_bit(desc->slice_id, drv_data->bitmap)) {
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mutex_unlock(&drv_data->lock);
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return 0;
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}
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act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT;
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ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
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ACTIVATE);
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if (ret) {
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mutex_unlock(&drv_data->lock);
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return ret;
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}
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__clear_bit(desc->slice_id, drv_data->bitmap);
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mutex_unlock(&drv_data->lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(llcc_slice_deactivate);
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/**
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* llcc_get_slice_id - return the slice id
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* @desc: Pointer to llcc slice descriptor
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*/
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int llcc_get_slice_id(struct llcc_slice_desc *desc)
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{
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if (IS_ERR_OR_NULL(desc))
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return -EINVAL;
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return desc->slice_id;
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}
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EXPORT_SYMBOL_GPL(llcc_get_slice_id);
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/**
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* llcc_get_slice_size - return the slice id
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* @desc: Pointer to llcc slice descriptor
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*/
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size_t llcc_get_slice_size(struct llcc_slice_desc *desc)
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{
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if (IS_ERR_OR_NULL(desc))
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return 0;
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return desc->slice_size;
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}
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EXPORT_SYMBOL_GPL(llcc_get_slice_size);
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static int qcom_llcc_cfg_program(struct platform_device *pdev)
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{
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int i;
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u32 attr1_cfg;
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u32 attr0_cfg;
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u32 attr1_val;
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u32 attr0_val;
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u32 max_cap_cacheline;
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u32 sz;
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int ret = 0;
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const struct llcc_slice_config *llcc_table;
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struct llcc_slice_desc desc;
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sz = drv_data->cfg_size;
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llcc_table = drv_data->cfg;
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for (i = 0; i < sz; i++) {
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attr1_cfg = LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id);
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attr0_cfg = LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id);
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attr1_val = llcc_table[i].cache_mode;
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attr1_val |= llcc_table[i].probe_target_ways <<
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ATTR1_PROBE_TARGET_WAYS_SHIFT;
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attr1_val |= llcc_table[i].fixed_size <<
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ATTR1_FIXED_SIZE_SHIFT;
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attr1_val |= llcc_table[i].priority <<
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ATTR1_PRIORITY_SHIFT;
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max_cap_cacheline = MAX_CAP_TO_BYTES(llcc_table[i].max_cap);
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/* LLCC instances can vary for each target.
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* The SW writes to broadcast register which gets propagated
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* to each llcc instace (llcc0,.. llccN).
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* Since the size of the memory is divided equally amongst the
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* llcc instances, we need to configure the max cap accordingly.
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*/
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max_cap_cacheline = max_cap_cacheline / drv_data->num_banks;
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max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT;
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attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT;
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attr0_val = llcc_table[i].res_ways & ATTR0_RES_WAYS_MASK;
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attr0_val |= llcc_table[i].bonus_ways << ATTR0_BONUS_WAYS_SHIFT;
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ret = regmap_write(drv_data->bcast_regmap, attr1_cfg,
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attr1_val);
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if (ret)
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return ret;
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ret = regmap_write(drv_data->bcast_regmap, attr0_cfg,
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attr0_val);
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if (ret)
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return ret;
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if (llcc_table[i].activate_on_init) {
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desc.slice_id = llcc_table[i].slice_id;
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ret = llcc_slice_activate(&desc);
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}
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}
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return ret;
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}
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static int qcom_llcc_remove(struct platform_device *pdev)
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{
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/* Set the global pointer to a error code to avoid referencing it */
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drv_data = ERR_PTR(-ENODEV);
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return 0;
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}
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static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev,
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const char *name)
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{
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struct resource *res;
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void __iomem *base;
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struct regmap_config llcc_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.fast_io = true,
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};
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
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if (!res)
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return ERR_PTR(-ENODEV);
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base))
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return ERR_CAST(base);
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llcc_regmap_config.name = name;
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return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config);
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}
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static int qcom_llcc_probe(struct platform_device *pdev)
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{
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u32 num_banks;
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struct device *dev = &pdev->dev;
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int ret, i;
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struct platform_device *llcc_edac;
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const struct qcom_llcc_config *cfg;
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const struct llcc_slice_config *llcc_cfg;
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u32 sz;
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drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
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if (!drv_data) {
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ret = -ENOMEM;
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goto err;
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}
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drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base");
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if (IS_ERR(drv_data->regmap)) {
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ret = PTR_ERR(drv_data->regmap);
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goto err;
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}
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drv_data->bcast_regmap =
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qcom_llcc_init_mmio(pdev, "llcc_broadcast_base");
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if (IS_ERR(drv_data->bcast_regmap)) {
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ret = PTR_ERR(drv_data->bcast_regmap);
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goto err;
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}
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ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0,
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&num_banks);
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if (ret)
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goto err;
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num_banks &= LLCC_LB_CNT_MASK;
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num_banks >>= LLCC_LB_CNT_SHIFT;
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drv_data->num_banks = num_banks;
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cfg = of_device_get_match_data(&pdev->dev);
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llcc_cfg = cfg->sct_data;
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sz = cfg->size;
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for (i = 0; i < sz; i++)
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if (llcc_cfg[i].slice_id > drv_data->max_slices)
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drv_data->max_slices = llcc_cfg[i].slice_id;
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drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32),
|
|
GFP_KERNEL);
|
|
if (!drv_data->offsets) {
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
for (i = 0; i < num_banks; i++)
|
|
drv_data->offsets[i] = i * BANK_OFFSET_STRIDE;
|
|
|
|
drv_data->bitmap = devm_kcalloc(dev,
|
|
BITS_TO_LONGS(drv_data->max_slices), sizeof(unsigned long),
|
|
GFP_KERNEL);
|
|
if (!drv_data->bitmap) {
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
drv_data->cfg = llcc_cfg;
|
|
drv_data->cfg_size = sz;
|
|
mutex_init(&drv_data->lock);
|
|
platform_set_drvdata(pdev, drv_data);
|
|
|
|
ret = qcom_llcc_cfg_program(pdev);
|
|
if (ret)
|
|
goto err;
|
|
|
|
drv_data->ecc_irq = platform_get_irq(pdev, 0);
|
|
if (drv_data->ecc_irq >= 0) {
|
|
llcc_edac = platform_device_register_data(&pdev->dev,
|
|
"qcom_llcc_edac", -1, drv_data,
|
|
sizeof(*drv_data));
|
|
if (IS_ERR(llcc_edac))
|
|
dev_err(dev, "Failed to register llcc edac driver\n");
|
|
}
|
|
|
|
return 0;
|
|
err:
|
|
drv_data = ERR_PTR(-ENODEV);
|
|
return ret;
|
|
}
|
|
|
|
static const struct of_device_id qcom_llcc_of_match[] = {
|
|
{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
|
|
{ .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
|
|
{ }
|
|
};
|
|
|
|
static struct platform_driver qcom_llcc_driver = {
|
|
.driver = {
|
|
.name = "qcom-llcc",
|
|
.of_match_table = qcom_llcc_of_match,
|
|
},
|
|
.probe = qcom_llcc_probe,
|
|
.remove = qcom_llcc_remove,
|
|
};
|
|
module_platform_driver(qcom_llcc_driver);
|
|
|
|
MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller");
|
|
MODULE_LICENSE("GPL v2");
|