Harigovindan P e3ff688123 drm/msm: update LANE_CTRL register value from default value ... LANE_CTRL register in latest version of DSI controller (v2.2) has additional functionality introduced to enable/disable HS signalling with default value set to enabled. To accommodate this change, LANE_CTRL register should be read and bit wise ORed to enable non continuous clock mode. Without this change, if register is written directly, HS signalling will be disabled resulting in black screen. Changes in v1: -Update LANE_CTRL register value Changes in v2: -Changing commit message accordingly. Signed-off-by: Harigovindan P <harigovi@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>		2020-01-07 08:26:30 -08:00
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phy	drm/msm/dsi: Add configuration for 28nm PLL on family B	2019-11-04 13:17:42 -08:00
pll	drm/msm: drop use of drmP.h	2019-09-03 16:16:57 -07:00
dsi_cfg.c	drm/msm: add DSI support for sc7180	2020-01-07 08:25:56 -08:00
dsi_cfg.h	drm/msm: add DSI support for sc7180	2020-01-07 08:25:56 -08:00
dsi_host.c	drm/msm: update LANE_CTRL register value from default value	2020-01-07 08:26:30 -08:00
dsi_manager.c	drm/msm/dsi: Delay drm_panel_enable() until dsi_mgr_bridge_enable()	2020-01-02 16:01:30 -08:00
dsi.c	Merge tag 'drm-msm-next-2019-06-25' of https://gitlab.freedesktop.org/drm/msm into drm-next	2019-06-28 10:16:40 +10:00
dsi.h	drm/msm/dsi: split clk rate setting and enable	2020-01-04 08:52:04 -08:00
dsi.xml.h	drm/msm: update generated headers	2018-08-10 18:49:18 -04:00
mmss_cc.xml.h	drm/msm: update generated headers	2018-08-10 18:49:18 -04:00
sfpb.xml.h	drm/msm: update generated headers	2018-08-10 18:49:18 -04:00