forked from Minki/linux
67dcdd4d3b
Create an environment for CXL plumbing unit tests. Especially when it comes to an algorithm for HDM Decoder (Host-managed Device Memory Decoder) programming, the availability of an in-kernel-tree emulation environment for CXL configuration complexity and corner cases speeds development and deters regressions. The approach taken mirrors what was done for tools/testing/nvdimm/. I.e. an external module, cxl_test.ko built out of the tools/testing/cxl/ directory, provides mock implementations of kernel APIs and kernel objects to simulate a real world device hierarchy. One feedback for the tools/testing/nvdimm/ proposal was "why not do this in QEMU?". In fact, the CXL development community has developed a QEMU model for CXL [1]. However, there are a few blocking issues that keep QEMU from being a tight fit for topology + provisioning unit tests: 1/ The QEMU community has yet to show interest in merging any of this support that has had patches on the list since November 2020. So, testing CXL to date involves building custom QEMU with out-of-tree patches. 2/ CXL mechanisms like cross-host-bridge interleave do not have a clear path to be emulated by QEMU without major infrastructure work. This is easier to achieve with the alloc_mock_res() approach taken in this patch to shortcut-define emulated system physical address ranges with interleave behavior. The QEMU enabling has been critical to get the driver off the ground, and may still move forward, but it does not address the ongoing needs of a regression testing environment and test driven development. This patch adds an ACPI CXL Platform definition with emulated CXL multi-ported host-bridges. A follow on patch adds emulated memory expander devices. Acked-by: Ben Widawsky <ben.widawsky@intel.com> Reported-by: Vishal Verma <vishal.l.verma@intel.com> Link: https://lore.kernel.org/r/20210202005948.241655-1-ben.widawsky@intel.com [1] Link: https://lore.kernel.org/r/163164680798.2831381.838684634806668012.stgit@dwillia2-desk3.amr.corp.intel.com Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
110 lines
2.6 KiB
C
110 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2021 Intel Corporation. All rights reserved. */
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#include <linux/platform_device.h>
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#include <linux/device.h>
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#include <linux/acpi.h>
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#include <linux/pci.h>
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#include <cxl.h>
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#include "test/mock.h"
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struct acpi_device *to_cxl_host_bridge(struct device *host, struct device *dev)
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{
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int index;
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struct acpi_device *adev, *found = NULL;
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struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
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if (ops && ops->is_mock_bridge(dev)) {
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found = ACPI_COMPANION(dev);
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goto out;
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}
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if (dev->bus == &platform_bus_type)
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goto out;
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adev = to_acpi_device(dev);
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if (!acpi_pci_find_root(adev->handle))
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goto out;
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if (strcmp(acpi_device_hid(adev), "ACPI0016") == 0) {
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found = adev;
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dev_dbg(host, "found host bridge %s\n", dev_name(&adev->dev));
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}
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out:
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put_cxl_mock_ops(index);
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return found;
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}
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static int match_add_root_port(struct pci_dev *pdev, void *data)
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{
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struct cxl_walk_context *ctx = data;
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struct pci_bus *root_bus = ctx->root;
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struct cxl_port *port = ctx->port;
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int type = pci_pcie_type(pdev);
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struct device *dev = ctx->dev;
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u32 lnkcap, port_num;
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int rc;
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if (pdev->bus != root_bus)
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return 0;
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if (!pci_is_pcie(pdev))
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return 0;
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if (type != PCI_EXP_TYPE_ROOT_PORT)
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return 0;
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if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP,
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&lnkcap) != PCIBIOS_SUCCESSFUL)
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return 0;
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/* TODO walk DVSEC to find component register base */
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port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap);
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rc = cxl_add_dport(port, &pdev->dev, port_num, CXL_RESOURCE_NONE);
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if (rc) {
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dev_err(dev, "failed to add dport: %s (%d)\n",
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dev_name(&pdev->dev), rc);
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ctx->error = rc;
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return rc;
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}
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ctx->count++;
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dev_dbg(dev, "add dport%d: %s\n", port_num, dev_name(&pdev->dev));
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return 0;
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}
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static int mock_add_root_port(struct platform_device *pdev, void *data)
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{
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struct cxl_walk_context *ctx = data;
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struct cxl_port *port = ctx->port;
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struct device *dev = ctx->dev;
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int rc;
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rc = cxl_add_dport(port, &pdev->dev, pdev->id, CXL_RESOURCE_NONE);
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if (rc) {
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dev_err(dev, "failed to add dport: %s (%d)\n",
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dev_name(&pdev->dev), rc);
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ctx->error = rc;
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return rc;
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}
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ctx->count++;
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dev_dbg(dev, "add dport%d: %s\n", pdev->id, dev_name(&pdev->dev));
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return 0;
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}
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int match_add_root_ports(struct pci_dev *dev, void *data)
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{
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int index, rc;
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struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
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struct platform_device *pdev = (struct platform_device *) dev;
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if (ops && ops->is_mock_port(pdev))
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rc = mock_add_root_port(pdev, data);
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else
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rc = match_add_root_port(dev, data);
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put_cxl_mock_ops(index);
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return rc;
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}
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