forked from Minki/linux
518bacf5a5
Pull x86 FPU updates from Ingo Molnar:
"The main changes in this cycle were:
- do a large round of simplifications after all CPUs do 'eager' FPU
context switching in v4.9: remove CR0 twiddling, remove leftover
eager/lazy bts, etc (Andy Lutomirski)
- more FPU code simplifications: remove struct fpu::counter, clarify
nomenclature, remove unnecessary arguments/functions and better
structure the code (Rik van Riel)"
* 'x86-fpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/fpu: Remove clts()
x86/fpu: Remove stts()
x86/fpu: Handle #NM without FPU emulation as an error
x86/fpu, lguest: Remove CR0.TS support
x86/fpu, kvm: Remove host CR0.TS manipulation
x86/fpu: Remove irq_ts_save() and irq_ts_restore()
x86/fpu: Stop saving and restoring CR0.TS in fpu__init_check_bugs()
x86/fpu: Get rid of two redundant clts() calls
x86/fpu: Finish excising 'eagerfpu'
x86/fpu: Split old_fpu & new_fpu handling into separate functions
x86/fpu: Remove 'cpu' argument from __cpu_invalidate_fpregs_state()
x86/fpu: Split old & new FPU code paths
x86/fpu: Remove __fpregs_(de)activate()
x86/fpu: Rename lazy restore functions to "register state valid"
x86/fpu, kvm: Remove KVM vcpu->fpu_counter
x86/fpu: Remove struct fpu::counter
x86/fpu: Remove use_eager_fpu()
x86/fpu: Remove the XFEATURE_MASK_EAGER/LAZY distinction
x86/fpu: Hard-disable lazy FPU mode
x86/crypto, x86/fpu: Remove X86_FEATURE_EAGER_FPU #ifdef from the crc32c code
82 lines
2.2 KiB
C
82 lines
2.2 KiB
C
#include <asm/paravirt.h>
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DEF_NATIVE(pv_irq_ops, irq_disable, "cli");
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DEF_NATIVE(pv_irq_ops, irq_enable, "sti");
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DEF_NATIVE(pv_irq_ops, restore_fl, "push %eax; popf");
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DEF_NATIVE(pv_irq_ops, save_fl, "pushf; pop %eax");
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DEF_NATIVE(pv_cpu_ops, iret, "iret");
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DEF_NATIVE(pv_mmu_ops, read_cr2, "mov %cr2, %eax");
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DEF_NATIVE(pv_mmu_ops, write_cr3, "mov %eax, %cr3");
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DEF_NATIVE(pv_mmu_ops, read_cr3, "mov %cr3, %eax");
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#if defined(CONFIG_PARAVIRT_SPINLOCKS)
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DEF_NATIVE(pv_lock_ops, queued_spin_unlock, "movb $0, (%eax)");
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DEF_NATIVE(pv_lock_ops, vcpu_is_preempted, "xor %eax, %eax");
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#endif
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unsigned paravirt_patch_ident_32(void *insnbuf, unsigned len)
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{
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/* arg in %eax, return in %eax */
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return 0;
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}
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unsigned paravirt_patch_ident_64(void *insnbuf, unsigned len)
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{
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/* arg in %edx:%eax, return in %edx:%eax */
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return 0;
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}
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extern bool pv_is_native_spin_unlock(void);
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extern bool pv_is_native_vcpu_is_preempted(void);
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unsigned native_patch(u8 type, u16 clobbers, void *ibuf,
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unsigned long addr, unsigned len)
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{
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const unsigned char *start, *end;
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unsigned ret;
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#define PATCH_SITE(ops, x) \
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case PARAVIRT_PATCH(ops.x): \
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start = start_##ops##_##x; \
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end = end_##ops##_##x; \
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goto patch_site
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switch (type) {
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PATCH_SITE(pv_irq_ops, irq_disable);
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PATCH_SITE(pv_irq_ops, irq_enable);
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PATCH_SITE(pv_irq_ops, restore_fl);
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PATCH_SITE(pv_irq_ops, save_fl);
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PATCH_SITE(pv_cpu_ops, iret);
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PATCH_SITE(pv_mmu_ops, read_cr2);
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PATCH_SITE(pv_mmu_ops, read_cr3);
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PATCH_SITE(pv_mmu_ops, write_cr3);
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#if defined(CONFIG_PARAVIRT_SPINLOCKS)
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case PARAVIRT_PATCH(pv_lock_ops.queued_spin_unlock):
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if (pv_is_native_spin_unlock()) {
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start = start_pv_lock_ops_queued_spin_unlock;
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end = end_pv_lock_ops_queued_spin_unlock;
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goto patch_site;
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}
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goto patch_default;
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case PARAVIRT_PATCH(pv_lock_ops.vcpu_is_preempted):
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if (pv_is_native_vcpu_is_preempted()) {
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start = start_pv_lock_ops_vcpu_is_preempted;
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end = end_pv_lock_ops_vcpu_is_preempted;
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goto patch_site;
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}
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goto patch_default;
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#endif
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default:
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patch_default:
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ret = paravirt_patch_default(type, clobbers, ibuf, addr, len);
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break;
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patch_site:
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ret = paravirt_patch_insns(ibuf, len, start, end);
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break;
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}
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#undef PATCH_SITE
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return ret;
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}
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